
Otilia Gabor
Examiner (ID: 2881)
| Most Active Art Unit | 2878 |
| Art Unit(s) | 2878, 2884 |
| Total Applications | 620 |
| Issued Applications | 492 |
| Pending Applications | 59 |
| Abandoned Applications | 69 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4363608
[patent_doc_number] => 06215703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'In order queue inactivity timer to improve DRAM arbiter operation'
[patent_app_type] => 1
[patent_app_number] => 9/205504
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/215/06215703.pdf
[firstpage_image] =>[orig_patent_app_number] => 205504
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205504 | In order queue inactivity timer to improve DRAM arbiter operation | Dec 3, 1998 | Issued |
Array
(
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[patent_doc_number] => 06009029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Circuit and method for antifuse stress test'
[patent_app_type] => 1
[patent_app_number] => 9/201204
[patent_app_country] => US
[patent_app_date] => 1998-11-30
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[pdf_file] => patents/06/009/06009029.pdf
[firstpage_image] =>[orig_patent_app_number] => 201204
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/201204 | Circuit and method for antifuse stress test | Nov 29, 1998 | Issued |
Array
(
[id] => 4170097
[patent_doc_number] => 06104640
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Electrically alterable non-violatile memory with N-bits per cell'
[patent_app_type] => 1
[patent_app_number] => 9/195201
[patent_app_country] => US
[patent_app_date] => 1998-11-18
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[pdf_file] => patents/06/104/06104640.pdf
[firstpage_image] =>[orig_patent_app_number] => 195201
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/195201 | Electrically alterable non-violatile memory with N-bits per cell | Nov 17, 1998 | Issued |
Array
(
[id] => 3964439
[patent_doc_number] => 05978306
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Memory device having a redundant memory block'
[patent_app_type] => 1
[patent_app_number] => 9/191805
[patent_app_country] => US
[patent_app_date] => 1998-11-13
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 191805
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/191805 | Memory device having a redundant memory block | Nov 12, 1998 | Issued |
Array
(
[id] => 3993997
[patent_doc_number] => 05949719
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Field programmable memory array'
[patent_app_type] => 1
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[patent_app_date] => 1998-11-12
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[pdf_file] => patents/05/949/05949719.pdf
[firstpage_image] =>[orig_patent_app_number] => 190905
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/190905 | Field programmable memory array | Nov 11, 1998 | Issued |
Array
(
[id] => 1463778
[patent_doc_number] => 06392947
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => B1
[patent_app_number] => 09/186315
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[pdf_file] => patents/06/392/06392947.pdf
[firstpage_image] =>[orig_patent_app_number] => 09186315
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186315 | Semiconductor memory device | Nov 3, 1998 | Issued |
Array
(
[id] => 4103002
[patent_doc_number] => 06134173
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[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Programmable logic array integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/184383
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[pdf_file] => patents/06/134/06134173.pdf
[firstpage_image] =>[orig_patent_app_number] => 184383
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/184383 | Programmable logic array integrated circuits | Nov 1, 1998 | Issued |
Array
(
[id] => 3970330
[patent_doc_number] => 05936907
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[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Method for detecting redunded defective addresses in a memory device with redundancy'
[patent_app_type] => 1
[patent_app_number] => 9/183469
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[patent_app_date] => 1998-10-30
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[pdf_file] => patents/05/936/05936907.pdf
[firstpage_image] =>[orig_patent_app_number] => 183469
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183469 | Method for detecting redunded defective addresses in a memory device with redundancy | Oct 29, 1998 | Issued |
Array
(
[id] => 4250700
[patent_doc_number] => 06081466
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Stress test mode entry at power up for low/zero power memories'
[patent_app_type] => 1
[patent_app_number] => 9/183451
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[pdf_file] => patents/06/081/06081466.pdf
[firstpage_image] =>[orig_patent_app_number] => 183451
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183451 | Stress test mode entry at power up for low/zero power memories | Oct 29, 1998 | Issued |
Array
(
[id] => 4159440
[patent_doc_number] => 06064599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Programmable logic array integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/179254
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[firstpage_image] =>[orig_patent_app_number] => 179254
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/179254 | Programmable logic array integrated circuits | Oct 25, 1998 | Issued |
Array
(
[id] => 3950810
[patent_doc_number] => 05930195
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[patent_title] => 'Semiconductor memory device'
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[firstpage_image] =>[orig_patent_app_number] => 179105
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/179105 | Semiconductor memory device | Oct 25, 1998 | Issued |
Array
(
[id] => 4096404
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Array
(
[id] => 3993701
[patent_doc_number] => 05949700
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[patent_title] => 'Five square vertical dynamic random access memory cell'
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Array
(
[id] => 4110664
[patent_doc_number] => 06097661
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[patent_title] => 'Pointer circuit with low surface requirement high speed and low power loss'
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[firstpage_image] =>[orig_patent_app_number] => 161004
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/161004 | Pointer circuit with low surface requirement high speed and low power loss | Sep 24, 1998 | Issued |
Array
(
[id] => 4231192
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[patent_title] => 'Integrated circuit with electrically programmable fuse resistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160404 | Integrated circuit with electrically programmable fuse resistor | Sep 24, 1998 | Issued |
Array
(
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Array
(
[id] => 4171318
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[patent_title] => 'Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151903 | Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors | Sep 10, 1998 | Issued |
Array
(
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/141204 | Method for forming multi-chip sensing device and device formed | Aug 26, 1998 | Issued |