Search

Otilia Gabor

Examiner (ID: 2881)

Most Active Art Unit
2878
Art Unit(s)
2878, 2884
Total Applications
620
Issued Applications
492
Pending Applications
59
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4363608 [patent_doc_number] => 06215703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'In order queue inactivity timer to improve DRAM arbiter operation' [patent_app_type] => 1 [patent_app_number] => 9/205504 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2955 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215703.pdf [firstpage_image] =>[orig_patent_app_number] => 205504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205504
In order queue inactivity timer to improve DRAM arbiter operation Dec 3, 1998 Issued
Array ( [id] => 4078185 [patent_doc_number] => 06009029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Circuit and method for antifuse stress test' [patent_app_type] => 1 [patent_app_number] => 9/201204 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4197 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009029.pdf [firstpage_image] =>[orig_patent_app_number] => 201204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/201204
Circuit and method for antifuse stress test Nov 29, 1998 Issued
Array ( [id] => 4170097 [patent_doc_number] => 06104640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Electrically alterable non-violatile memory with N-bits per cell' [patent_app_type] => 1 [patent_app_number] => 9/195201 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7037 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104640.pdf [firstpage_image] =>[orig_patent_app_number] => 195201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195201
Electrically alterable non-violatile memory with N-bits per cell Nov 17, 1998 Issued
Array ( [id] => 3964439 [patent_doc_number] => 05978306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Memory device having a redundant memory block' [patent_app_type] => 1 [patent_app_number] => 9/191805 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4519 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978306.pdf [firstpage_image] =>[orig_patent_app_number] => 191805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191805
Memory device having a redundant memory block Nov 12, 1998 Issued
Array ( [id] => 3993997 [patent_doc_number] => 05949719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Field programmable memory array' [patent_app_type] => 1 [patent_app_number] => 9/190905 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 52 [patent_no_of_words] => 24699 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949719.pdf [firstpage_image] =>[orig_patent_app_number] => 190905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190905
Field programmable memory array Nov 11, 1998 Issued
Array ( [id] => 1463778 [patent_doc_number] => 06392947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/186315 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4587 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392947.pdf [firstpage_image] =>[orig_patent_app_number] => 09186315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186315
Semiconductor memory device Nov 3, 1998 Issued
Array ( [id] => 4103002 [patent_doc_number] => 06134173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/184383 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 14873 [patent_no_of_claims] => 108 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134173.pdf [firstpage_image] =>[orig_patent_app_number] => 184383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184383
Programmable logic array integrated circuits Nov 1, 1998 Issued
Array ( [id] => 3970330 [patent_doc_number] => 05936907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method for detecting redunded defective addresses in a memory device with redundancy' [patent_app_type] => 1 [patent_app_number] => 9/183469 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3592 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936907.pdf [firstpage_image] =>[orig_patent_app_number] => 183469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183469
Method for detecting redunded defective addresses in a memory device with redundancy Oct 29, 1998 Issued
Array ( [id] => 4250700 [patent_doc_number] => 06081466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Stress test mode entry at power up for low/zero power memories' [patent_app_type] => 1 [patent_app_number] => 9/183451 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081466.pdf [firstpage_image] =>[orig_patent_app_number] => 183451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183451
Stress test mode entry at power up for low/zero power memories Oct 29, 1998 Issued
Array ( [id] => 4159440 [patent_doc_number] => 06064599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/179254 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 14874 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064599.pdf [firstpage_image] =>[orig_patent_app_number] => 179254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179254
Programmable logic array integrated circuits Oct 25, 1998 Issued
Array ( [id] => 3950810 [patent_doc_number] => 05930195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/179105 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5872 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930195.pdf [firstpage_image] =>[orig_patent_app_number] => 179105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179105
Semiconductor memory device Oct 25, 1998 Issued
Array ( [id] => 4096404 [patent_doc_number] => 06018490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/169332 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 14872 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018490.pdf [firstpage_image] =>[orig_patent_app_number] => 169332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169332
Programmable logic array integrated circuits Oct 8, 1998 Issued
Array ( [id] => 3993701 [patent_doc_number] => 05949700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Five square vertical dynamic random access memory cell' [patent_app_type] => 1 [patent_app_number] => 9/165503 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 3348 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949700.pdf [firstpage_image] =>[orig_patent_app_number] => 165503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165503
Five square vertical dynamic random access memory cell Oct 1, 1998 Issued
Array ( [id] => 4110664 [patent_doc_number] => 06097661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Pointer circuit with low surface requirement high speed and low power loss' [patent_app_type] => 1 [patent_app_number] => 9/161004 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 13338 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097661.pdf [firstpage_image] =>[orig_patent_app_number] => 161004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161004
Pointer circuit with low surface requirement high speed and low power loss Sep 24, 1998 Issued
Array ( [id] => 4231192 [patent_doc_number] => 06088256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Integrated circuit with electrically programmable fuse resistor' [patent_app_type] => 1 [patent_app_number] => 9/160404 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088256.pdf [firstpage_image] =>[orig_patent_app_number] => 160404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160404
Integrated circuit with electrically programmable fuse resistor Sep 24, 1998 Issued
Array ( [id] => 4116644 [patent_doc_number] => 06023439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/156036 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 14884 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023439.pdf [firstpage_image] =>[orig_patent_app_number] => 156036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156036
Programmable logic array integrated circuits Sep 16, 1998 Issued
Array ( [id] => 4171318 [patent_doc_number] => 06115281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors' [patent_app_type] => 1 [patent_app_number] => 9/151903 [patent_app_country] => US [patent_app_date] => 1998-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7568 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115281.pdf [firstpage_image] =>[orig_patent_app_number] => 151903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151903
Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors Sep 10, 1998 Issued
Array ( [id] => 4120742 [patent_doc_number] => 06058064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor memory devices having shared data line contacts' [patent_app_type] => 1 [patent_app_number] => 9/145905 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2688 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058064.pdf [firstpage_image] =>[orig_patent_app_number] => 145905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145905
Semiconductor memory devices having shared data line contacts Sep 1, 1998 Issued
Array ( [id] => 4229576 [patent_doc_number] => 06111776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Compact optical random access memory having multiple reflections' [patent_app_type] => 1 [patent_app_number] => 9/141335 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111776.pdf [firstpage_image] =>[orig_patent_app_number] => 141335 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141335
Compact optical random access memory having multiple reflections Aug 26, 1998 Issued
Array ( [id] => 4261438 [patent_doc_number] => 06137708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method for forming multi-chip sensing device and device formed' [patent_app_type] => 1 [patent_app_number] => 9/141204 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137708.pdf [firstpage_image] =>[orig_patent_app_number] => 141204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141204
Method for forming multi-chip sensing device and device formed Aug 26, 1998 Issued
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