Otilia Gabor

Array ( [id] => 4048109 [patent_doc_number] => 05995435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Semiconductor memory device having controllable supplying capability of internal voltage' [patent_app_type] => 1 [patent_app_number] => 9/137707 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 8779 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995435.pdf [firstpage_image] =>[orig_patent_app_number] => 137707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4231176 [patent_doc_number] => 06088255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor device with prompt timing stabilization' [patent_app_type] => 1 [patent_app_number] => 9/137101 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 158 [patent_no_of_words] => 22049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088255.pdf [firstpage_image] =>[orig_patent_app_number] => 137101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144080 [patent_doc_number] => 06034880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Embedded memory device and method of performing a burn-in process on the embedded memory device' [patent_app_type] => 1 [patent_app_number] => 9/136502 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3416 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034880.pdf [firstpage_image] =>[orig_patent_app_number] => 136502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155498 [patent_doc_number] => 06031786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Operation control circuits and methods for integrated circuit memory devices' [patent_app_type] => 1 [patent_app_number] => 9/134807 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4282 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031786.pdf [firstpage_image] =>[orig_patent_app_number] => 134807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4010476 [patent_doc_number] => 05923584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Dual poly integrated circuit interconnect' [patent_app_type] => 1 [patent_app_number] => 9/134005 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 2770 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923584.pdf [firstpage_image] =>[orig_patent_app_number] => 134005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4231287 [patent_doc_number] => 06088261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 9/132502 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 38 [patent_no_of_words] => 28729 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088261.pdf [firstpage_image] =>[orig_patent_app_number] => 132502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3964080 [patent_doc_number] => 05978280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity' [patent_app_type] => 1 [patent_app_number] => 9/132100 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2967 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978280.pdf [firstpage_image] =>[orig_patent_app_number] => 132100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395380 [patent_doc_number] => 06278645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'High speed video frame buffer' [patent_app_type] => 1 [patent_app_number] => 9/129293 [patent_app_country] => US [patent_app_date] => 1998-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15666 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278645.pdf [firstpage_image] =>[orig_patent_app_number] => 129293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159847 [patent_doc_number] => 06064626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Peripheral buses for integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/127605 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5159 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064626.pdf [firstpage_image] =>[orig_patent_app_number] => 127605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108891 [patent_doc_number] => 06049490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Decoded signal comparison circuit' [patent_app_type] => 1 [patent_app_number] => 9/126302 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5945 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049490.pdf [firstpage_image] =>[orig_patent_app_number] => 126302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4064835 [patent_doc_number] => 05969984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Level converting circuit for converting level of an input signal, internal potential generating circuit for generating internal potential, internal potential generating unit generating internal potential, highly reliable semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/124508 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 75 [patent_no_of_words] => 23987 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969984.pdf [firstpage_image] =>[orig_patent_app_number] => 124508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4097176 [patent_doc_number] => 06026049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Semiconductor memory with sensing stability' [patent_app_type] => 1 [patent_app_number] => 9/123302 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2571 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026049.pdf [firstpage_image] =>[orig_patent_app_number] => 123302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4096847 [patent_doc_number] => 06026028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Hot carrier injection programming and negative gate voltage channel erase flash EEPROM structure' [patent_app_type] => 1 [patent_app_number] => 9/123305 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2135 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026028.pdf [firstpage_image] =>[orig_patent_app_number] => 123305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4192033 [patent_doc_number] => 06038180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Semiconductor memory capable of detecting memory cells with small margins as well as sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/120302 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4639 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038180.pdf [firstpage_image] =>[orig_patent_app_number] => 120302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3963780 [patent_doc_number] => 05978260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of time multiplexing a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 9/119534 [patent_app_country] => US [patent_app_date] => 1998-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 81 [patent_no_of_words] => 25744 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978260.pdf [firstpage_image] =>[orig_patent_app_number] => 119534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152732 [patent_doc_number] => 06061264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Self-aligned fuse structure and method with anti-reflective coating' [patent_app_type] => 1 [patent_app_number] => 9/118602 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5014 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061264.pdf [firstpage_image] =>[orig_patent_app_number] => 118602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054599 [patent_doc_number] => 05912852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Synchronous memory test method' [patent_app_type] => 1 [patent_app_number] => 9/115001 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 31215 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912852.pdf [firstpage_image] =>[orig_patent_app_number] => 115001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126952 [patent_doc_number] => 06046948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Low word line to bit line short circuit standby current semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/114600 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4633 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046948.pdf [firstpage_image] =>[orig_patent_app_number] => 114600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114952 [patent_doc_number] => 06052311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Electrically erasable programmable read only flash memory' [patent_app_type] => 1 [patent_app_number] => 9/114004 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2340 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052311.pdf [firstpage_image] =>[orig_patent_app_number] => 114004 [rel_patent_id] =>[rel_patent_doc_number] =>)