
Otilia Gabor
Examiner (ID: 2881)
| Most Active Art Unit | 2878 |
| Art Unit(s) | 2878, 2884 |
| Total Applications | 620 |
| Issued Applications | 492 |
| Pending Applications | 59 |
| Abandoned Applications | 69 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4318077
[patent_doc_number] => 06327204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Method of storing information in a memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/722023
[patent_app_country] => US
[patent_app_date] => 2000-11-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/327/06327204.pdf
[firstpage_image] =>[orig_patent_app_number] => 722023
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/722023 | Method of storing information in a memory cell | Nov 26, 2000 | Issued |
Array
(
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[patent_doc_number] => 06377495
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Apparatus and method for providing a bias to read memory elements'
[patent_app_type] => B1
[patent_app_number] => 09/718821
[patent_app_country] => US
[patent_app_date] => 2000-11-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/377/06377495.pdf
[firstpage_image] =>[orig_patent_app_number] => 09718821
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/718821 | Apparatus and method for providing a bias to read memory elements | Nov 21, 2000 | Issued |
Array
(
[id] => 4344636
[patent_doc_number] => 06314021
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Nonvolatile semiconductor memory device and semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/715141
[patent_app_country] => US
[patent_app_date] => 2000-11-20
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[patent_drawing_sheets_cnt] => 30
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[pdf_file] => patents/06/314/06314021.pdf
[firstpage_image] =>[orig_patent_app_number] => 715141
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715141 | Nonvolatile semiconductor memory device and semiconductor integrated circuit | Nov 19, 2000 | Issued |
Array
(
[id] => 1443007
[patent_doc_number] => 06335884
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Semiconductor memory device and defect remedying method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/714268
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/335/06335884.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714268
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714268 | Semiconductor memory device and defect remedying method thereof | Nov 16, 2000 | Issued |
Array
(
[id] => 1570381
[patent_doc_number] => 06377500
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Memory system with a non-volatile memory, having address translating function'
[patent_app_type] => B1
[patent_app_number] => 09/708423
[patent_app_country] => US
[patent_app_date] => 2000-11-09
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[pdf_file] => patents/06/377/06377500.pdf
[firstpage_image] =>[orig_patent_app_number] => 09708423
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/708423 | Memory system with a non-volatile memory, having address translating function | Nov 8, 2000 | Issued |
Array
(
[id] => 4344892
[patent_doc_number] => 06314036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Method and apparatus for efficiently testing RAMBUS memory devices'
[patent_app_type] => 1
[patent_app_number] => 9/708692
[patent_app_country] => US
[patent_app_date] => 2000-11-07
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[pdf_file] => patents/06/314/06314036.pdf
[firstpage_image] =>[orig_patent_app_number] => 708692
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/708692 | Method and apparatus for efficiently testing RAMBUS memory devices | Nov 6, 2000 | Issued |
Array
(
[id] => 4329641
[patent_doc_number] => 06331953
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-18
[patent_title] => 'Intelligent ramped gate and ramped drain erasure for non-volatile memory cells'
[patent_app_type] => 1
[patent_app_number] => 9/697813
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[patent_app_date] => 2000-10-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/331/06331953.pdf
[firstpage_image] =>[orig_patent_app_number] => 697813
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/697813 | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells | Oct 25, 2000 | Issued |
Array
(
[id] => 4283351
[patent_doc_number] => 06307795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-23
[patent_title] => 'Semiconductor memory having multiple redundant columns with offset segmentation boundaries'
[patent_app_type] => 1
[patent_app_number] => 9/695986
[patent_app_country] => US
[patent_app_date] => 2000-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/307/06307795.pdf
[firstpage_image] =>[orig_patent_app_number] => 695986
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/695986 | Semiconductor memory having multiple redundant columns with offset segmentation boundaries | Oct 25, 2000 | Issued |
Array
(
[id] => 4366669
[patent_doc_number] => 06292385
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Ferroelectric random access memory'
[patent_app_type] => 1
[patent_app_number] => 9/676521
[patent_app_country] => US
[patent_app_date] => 2000-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/06/292/06292385.pdf
[firstpage_image] =>[orig_patent_app_number] => 676521
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/676521 | Ferroelectric random access memory | Sep 28, 2000 | Issued |
Array
(
[id] => 1567613
[patent_doc_number] => 06339544
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-15
[patent_title] => 'Method to enhance performance of thermal resistor device'
[patent_app_type] => B1
[patent_app_number] => 09/676317
[patent_app_country] => US
[patent_app_date] => 2000-09-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/339/06339544.pdf
[firstpage_image] =>[orig_patent_app_number] => 09676317
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/676317 | Method to enhance performance of thermal resistor device | Sep 28, 2000 | Issued |
Array
(
[id] => 4317867
[patent_doc_number] => 06327193
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Mixed signal method for display deflection signal generation for low cost displays'
[patent_app_type] => 1
[patent_app_number] => 9/670215
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[patent_app_date] => 2000-09-25
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[pdf_file] => patents/06/327/06327193.pdf
[firstpage_image] =>[orig_patent_app_number] => 670215
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/670215 | Mixed signal method for display deflection signal generation for low cost displays | Sep 24, 2000 | Issued |
Array
(
[id] => 4329468
[patent_doc_number] => 06331942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-18
[patent_title] => 'Content addressable memory cell and design methodology utilizing grounding circuitry'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/658543 | Content addressable memory cell and design methodology utilizing grounding circuitry | Sep 8, 2000 | Issued |
Array
(
[id] => 4380787
[patent_doc_number] => 06275413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-14
[patent_title] => 'Architecture of a non-volatile electrically erasable and programmable memory'
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[patent_app_number] => 9/657319
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[firstpage_image] =>[orig_patent_app_number] => 657319
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Array
(
[id] => 4290950
[patent_doc_number] => 06282121
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[patent_issue_date] => 2001-08-28
[patent_title] => 'Flash memory device with program status detection circuitry and the method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/656321 | Flash memory device with program status detection circuitry and the method thereof | Sep 5, 2000 | Issued |
Array
(
[id] => 4393538
[patent_doc_number] => 06304510
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[patent_title] => 'Memory device address decoding'
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Array
(
[id] => 4283281
[patent_doc_number] => 06307790
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[patent_issue_date] => 2001-10-23
[patent_title] => 'Read compression in a memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/651641 | Read compression in a memory | Aug 29, 2000 | Issued |
Array
(
[id] => 4419005
[patent_doc_number] => 06301144
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Array
(
[id] => 4329757
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/641722 | Nonvolatile semiconductor memory device and method for using the same | Aug 20, 2000 | Issued |
Array
(
[id] => 4318070
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[patent_issue_date] => 2001-06-26
[patent_title] => 'Floating gate MOS transistor charge injection circuit and computation devices incorporating it'
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Array
(
[id] => 4298710
[patent_doc_number] => 06269043
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[patent_title] => 'Power conservation system employing a snooze mode'
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[pdf_file] => patents/06/269/06269043.pdf
[firstpage_image] =>[orig_patent_app_number] => 629715
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/629715 | Power conservation system employing a snooze mode | Jul 30, 2000 | Issued |