Search

Otilia Gabor

Examiner (ID: 2881)

Most Active Art Unit
2878
Art Unit(s)
2878, 2884
Total Applications
620
Issued Applications
492
Pending Applications
59
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4318077 [patent_doc_number] => 06327204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method of storing information in a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/722023 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2146 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327204.pdf [firstpage_image] =>[orig_patent_app_number] => 722023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722023
Method of storing information in a memory cell Nov 26, 2000 Issued
Array ( [id] => 1570358 [patent_doc_number] => 06377495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Apparatus and method for providing a bias to read memory elements' [patent_app_type] => B1 [patent_app_number] => 09/718821 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377495.pdf [firstpage_image] =>[orig_patent_app_number] => 09718821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/718821
Apparatus and method for providing a bias to read memory elements Nov 21, 2000 Issued
Array ( [id] => 4344636 [patent_doc_number] => 06314021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Nonvolatile semiconductor memory device and semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/715141 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 50 [patent_no_of_words] => 15583 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314021.pdf [firstpage_image] =>[orig_patent_app_number] => 715141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715141
Nonvolatile semiconductor memory device and semiconductor integrated circuit Nov 19, 2000 Issued
Array ( [id] => 1443007 [patent_doc_number] => 06335884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor memory device and defect remedying method thereof' [patent_app_type] => B1 [patent_app_number] => 09/714268 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 117 [patent_figures_cnt] => 163 [patent_no_of_words] => 51428 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335884.pdf [firstpage_image] =>[orig_patent_app_number] => 09714268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714268
Semiconductor memory device and defect remedying method thereof Nov 16, 2000 Issued
Array ( [id] => 1570381 [patent_doc_number] => 06377500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Memory system with a non-volatile memory, having address translating function' [patent_app_type] => B1 [patent_app_number] => 09/708423 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 15078 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377500.pdf [firstpage_image] =>[orig_patent_app_number] => 09708423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708423
Memory system with a non-volatile memory, having address translating function Nov 8, 2000 Issued
Array ( [id] => 4344892 [patent_doc_number] => 06314036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method and apparatus for efficiently testing RAMBUS memory devices' [patent_app_type] => 1 [patent_app_number] => 9/708692 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6180 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314036.pdf [firstpage_image] =>[orig_patent_app_number] => 708692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708692
Method and apparatus for efficiently testing RAMBUS memory devices Nov 6, 2000 Issued
Array ( [id] => 4329641 [patent_doc_number] => 06331953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Intelligent ramped gate and ramped drain erasure for non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/697813 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 10475 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331953.pdf [firstpage_image] =>[orig_patent_app_number] => 697813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697813
Intelligent ramped gate and ramped drain erasure for non-volatile memory cells Oct 25, 2000 Issued
Array ( [id] => 4283351 [patent_doc_number] => 06307795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Semiconductor memory having multiple redundant columns with offset segmentation boundaries' [patent_app_type] => 1 [patent_app_number] => 9/695986 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5777 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307795.pdf [firstpage_image] =>[orig_patent_app_number] => 695986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/695986
Semiconductor memory having multiple redundant columns with offset segmentation boundaries Oct 25, 2000 Issued
Array ( [id] => 4366669 [patent_doc_number] => 06292385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Ferroelectric random access memory' [patent_app_type] => 1 [patent_app_number] => 9/676521 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14202 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292385.pdf [firstpage_image] =>[orig_patent_app_number] => 676521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676521
Ferroelectric random access memory Sep 28, 2000 Issued
Array ( [id] => 1567613 [patent_doc_number] => 06339544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method to enhance performance of thermal resistor device' [patent_app_type] => B1 [patent_app_number] => 09/676317 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6158 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339544.pdf [firstpage_image] =>[orig_patent_app_number] => 09676317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676317
Method to enhance performance of thermal resistor device Sep 28, 2000 Issued
Array ( [id] => 4317867 [patent_doc_number] => 06327193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Mixed signal method for display deflection signal generation for low cost displays' [patent_app_type] => 1 [patent_app_number] => 9/670215 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7159 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327193.pdf [firstpage_image] =>[orig_patent_app_number] => 670215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670215
Mixed signal method for display deflection signal generation for low cost displays Sep 24, 2000 Issued
Array ( [id] => 4329468 [patent_doc_number] => 06331942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Content addressable memory cell and design methodology utilizing grounding circuitry' [patent_app_type] => 1 [patent_app_number] => 9/658543 [patent_app_country] => US [patent_app_date] => 2000-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10628 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331942.pdf [firstpage_image] =>[orig_patent_app_number] => 658543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658543
Content addressable memory cell and design methodology utilizing grounding circuitry Sep 8, 2000 Issued
Array ( [id] => 4380787 [patent_doc_number] => 06275413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Architecture of a non-volatile electrically erasable and programmable memory' [patent_app_type] => 1 [patent_app_number] => 9/657319 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5365 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275413.pdf [firstpage_image] =>[orig_patent_app_number] => 657319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657319
Architecture of a non-volatile electrically erasable and programmable memory Sep 6, 2000 Issued
Array ( [id] => 4290950 [patent_doc_number] => 06282121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Flash memory device with program status detection circuitry and the method thereof' [patent_app_type] => 1 [patent_app_number] => 9/656321 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 10249 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282121.pdf [firstpage_image] =>[orig_patent_app_number] => 656321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656321
Flash memory device with program status detection circuitry and the method thereof Sep 5, 2000 Issued
Array ( [id] => 4393538 [patent_doc_number] => 06304510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Memory device address decoding' [patent_app_type] => 1 [patent_app_number] => 9/652617 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4348 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304510.pdf [firstpage_image] =>[orig_patent_app_number] => 652617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652617
Memory device address decoding Aug 30, 2000 Issued
Array ( [id] => 4283281 [patent_doc_number] => 06307790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Read compression in a memory' [patent_app_type] => 1 [patent_app_number] => 9/651641 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3650 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307790.pdf [firstpage_image] =>[orig_patent_app_number] => 651641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651641
Read compression in a memory Aug 29, 2000 Issued
Array ( [id] => 4419005 [patent_doc_number] => 06301144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/650745 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4967 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301144.pdf [firstpage_image] =>[orig_patent_app_number] => 650745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650745
Semiconductor memory device Aug 29, 2000 Issued
Array ( [id] => 4329757 [patent_doc_number] => 06331960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Nonvolatile semiconductor memory device and method for using the same' [patent_app_type] => 1 [patent_app_number] => 9/641722 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 9469 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331960.pdf [firstpage_image] =>[orig_patent_app_number] => 641722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/641722
Nonvolatile semiconductor memory device and method for using the same Aug 20, 2000 Issued
Array ( [id] => 4318070 [patent_doc_number] => 06252802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Floating gate MOS transistor charge injection circuit and computation devices incorporating it' [patent_app_type] => 1 [patent_app_number] => 9/636397 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3078 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252802.pdf [firstpage_image] =>[orig_patent_app_number] => 636397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636397
Floating gate MOS transistor charge injection circuit and computation devices incorporating it Aug 8, 2000 Issued
Array ( [id] => 4298710 [patent_doc_number] => 06269043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Power conservation system employing a snooze mode' [patent_app_type] => 1 [patent_app_number] => 9/629715 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3673 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269043.pdf [firstpage_image] =>[orig_patent_app_number] => 629715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629715
Power conservation system employing a snooze mode Jul 30, 2000 Issued
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