
Otilia Gabor
Examiner (ID: 2881)
| Most Active Art Unit | 2878 |
| Art Unit(s) | 2878, 2884 |
| Total Applications | 620 |
| Issued Applications | 492 |
| Pending Applications | 59 |
| Abandoned Applications | 69 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4185872
[patent_doc_number] => 06141292
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Clock generating circuits that utilize analog pump signals to provide fast synchronization and reduced delay skew'
[patent_app_type] => 1
[patent_app_number] => 9/383805
[patent_app_country] => US
[patent_app_date] => 1999-08-26
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[pdf_file] => patents/06/141/06141292.pdf
[firstpage_image] =>[orig_patent_app_number] => 383805
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/383805 | Clock generating circuits that utilize analog pump signals to provide fast synchronization and reduced delay skew | Aug 25, 1999 | Issued |
Array
(
[id] => 4305248
[patent_doc_number] => 06236608
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Technique to improve the source leakage of flash EPROM cells during source erase'
[patent_app_type] => 1
[patent_app_number] => 9/375702
[patent_app_country] => US
[patent_app_date] => 1999-08-16
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[pdf_file] => patents/06/236/06236608.pdf
[firstpage_image] =>[orig_patent_app_number] => 375702
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375702 | Technique to improve the source leakage of flash EPROM cells during source erase | Aug 15, 1999 | Issued |
Array
(
[id] => 4305030
[patent_doc_number] => 06236592
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[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Floating gate MOS transistor charge injection circuit and computation devices incorporating it'
[patent_app_type] => 1
[patent_app_number] => 9/373813
[patent_app_country] => US
[patent_app_date] => 1999-08-13
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[firstpage_image] =>[orig_patent_app_number] => 373813
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373813 | Floating gate MOS transistor charge injection circuit and computation devices incorporating it | Aug 12, 1999 | Issued |
Array
(
[id] => 4170248
[patent_doc_number] => 06108263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Memory system, method for verifying data stored in a memory system after a write cycle and method for writing to a memory system'
[patent_app_type] => 1
[patent_app_number] => 9/373305
[patent_app_country] => US
[patent_app_date] => 1999-08-12
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[pdf_file] => patents/06/108/06108263.pdf
[firstpage_image] =>[orig_patent_app_number] => 373305
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373305 | Memory system, method for verifying data stored in a memory system after a write cycle and method for writing to a memory system | Aug 11, 1999 | Issued |
Array
(
[id] => 4169933
[patent_doc_number] => 06108242
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Flash memory with split gate structure and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/371702
[patent_app_country] => US
[patent_app_date] => 1999-08-10
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[pdf_file] => patents/06/108/06108242.pdf
[firstpage_image] =>[orig_patent_app_number] => 371702
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/371702 | Flash memory with split gate structure and method of fabricating the same | Aug 9, 1999 | Issued |
Array
(
[id] => 4197121
[patent_doc_number] => 06160744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Semiconductor memory device and defect remedying method thereof'
[patent_app_type] => 1
[patent_app_number] => 9/361203
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[firstpage_image] =>[orig_patent_app_number] => 361203
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/361203 | Semiconductor memory device and defect remedying method thereof | Jul 26, 1999 | Issued |
Array
(
[id] => 4309133
[patent_doc_number] => 06198663
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Non-volatile semiconductor memory IC'
[patent_app_type] => 1
[patent_app_number] => 9/361904
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[pdf_file] => patents/06/198/06198663.pdf
[firstpage_image] =>[orig_patent_app_number] => 361904
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/361904 | Non-volatile semiconductor memory IC | Jul 26, 1999 | Issued |
Array
(
[id] => 4252531
[patent_doc_number] => 06166984
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Non-volatile counter'
[patent_app_type] => 1
[patent_app_number] => 9/360404
[patent_app_country] => US
[patent_app_date] => 1999-07-23
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[pdf_file] => patents/06/166/06166984.pdf
[firstpage_image] =>[orig_patent_app_number] => 360404
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/360404 | Non-volatile counter | Jul 22, 1999 | Issued |
Array
(
[id] => 4266133
[patent_doc_number] => 06208569
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Method of and apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/356805
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[patent_app_date] => 1999-07-20
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[firstpage_image] =>[orig_patent_app_number] => 356805
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/356805 | Method of and apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device | Jul 19, 1999 | Issued |
Array
(
[id] => 4095891
[patent_doc_number] => 06163489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Semiconductor memory having multiple redundant columns with offset segmentation boundaries'
[patent_app_type] => 1
[patent_app_number] => 9/354304
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[patent_app_date] => 1999-07-16
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Array
(
[id] => 4247479
[patent_doc_number] => 06118717
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Method and apparatus for loading directly onto bit lines in a dynamic random access memory'
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[patent_app_number] => 9/354401
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354401 | Method and apparatus for loading directly onto bit lines in a dynamic random access memory | Jul 14, 1999 | Issued |
Array
(
[id] => 4393814
[patent_doc_number] => 06295231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'High-speed cycle clock-synchronous memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354102 | High-speed cycle clock-synchronous memory device | Jul 14, 1999 | Issued |
Array
(
[id] => 4170262
[patent_doc_number] => 06104650
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Sacrifice read test mode'
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[patent_app_number] => 9/350602
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Array
(
[id] => 4250625
[patent_doc_number] => 06144598
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[patent_title] => 'Method and apparatus for efficiently testing rambus memory devices'
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Array
(
[id] => 4169909
[patent_doc_number] => 06108241
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/345905 | Leakage detection in flash memory cell | Jun 30, 1999 | Issued |
Array
(
[id] => 4309496
[patent_doc_number] => 06185119
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[patent_title] => 'Analog memory IC with fully differential signal path'
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Array
(
[id] => 4230667
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Array
(
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[patent_title] => 'Voltage pump switch'
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Array
(
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[patent_title] => 'Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook'
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Array
(
[id] => 4425598
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[firstpage_image] =>[orig_patent_app_number] => 318895
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/318895 | Segmented column memory device voltage steering technique | May 25, 1999 | Issued |