Pablo S. Huerta

Array ( [id] => 8847739 [patent_doc_number] => 08456929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Circuits, systems, and methods for dynamic voltage level shifting' [patent_app_type] => utility [patent_app_number] => 12/755446 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4366 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12755446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8068247 [patent_doc_number] => 20110242894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD AND SYSTEM TO ISOLATE MEMORY MODULES IN A SOLID STATE DRIVE' [patent_app_type] => utility [patent_app_number] => 12/755220 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3793 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242894.pdf [firstpage_image] =>[orig_patent_app_number] => 12755220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6494755 [patent_doc_number] => 20100259972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'SEMICONDUCTOR MEMORY AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/755002 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10607 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259972.pdf [firstpage_image] =>[orig_patent_app_number] => 12755002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6549750 [patent_doc_number] => 20100271879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/754206 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7747 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271879.pdf [firstpage_image] =>[orig_patent_app_number] => 12754206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8399807 [patent_doc_number] => 08270194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Distributed flash memory storage manager systems' [patent_app_type] => utility [patent_app_number] => 12/754376 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 6882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8068305 [patent_doc_number] => 20110242874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'RESISTIVE MEMORY AND METHOD FOR CONTROLLING OPERATIONS OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/753316 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9098 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242874.pdf [firstpage_image] =>[orig_patent_app_number] => 12753316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5934697 [patent_doc_number] => 20110211410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/753606 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3934 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20110211410.pdf [firstpage_image] =>[orig_patent_app_number] => 12753606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8068291 [patent_doc_number] => 20110242880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY' [patent_app_type] => utility [patent_app_number] => 12/753809 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242880.pdf [firstpage_image] =>[orig_patent_app_number] => 12753809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6267343 [patent_doc_number] => 20100254196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'SEMICONDUCTOR DEVICE TESTING MEMORY CELLS AND TEST METHOD' [patent_app_type] => utility [patent_app_number] => 12/753186 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3489 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20100254196.pdf [firstpage_image] =>[orig_patent_app_number] => 12753186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147872 [patent_doc_number] => 20110019492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/752646 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8995 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20110019492.pdf [firstpage_image] =>[orig_patent_app_number] => 12752646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8068245 [patent_doc_number] => 20110242901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'LIFETIME MARKERS FOR MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/751630 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9581 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242901.pdf [firstpage_image] =>[orig_patent_app_number] => 12751630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8318517 [patent_doc_number] => 08233306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-31 [patent_title] => 'Memory program circuit' [patent_app_type] => utility [patent_app_number] => 12/751764 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4488 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6267366 [patent_doc_number] => 20100254202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'SYSTEM HAVING A PLURALITY OF MEMORY DEVICES AND DATA TRANSFER METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 12/751410 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 33327 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20100254202.pdf [firstpage_image] =>[orig_patent_app_number] => 12751410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6403606 [patent_doc_number] => 20100165727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'PHASE CHANGE MATERIAL MEMORY HAVING NO ERASE CYCLE' [patent_app_type] => utility [patent_app_number] => 12/650682 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2945 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165727.pdf [firstpage_image] =>[orig_patent_app_number] => 12650682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6403605 [patent_doc_number] => 20100165726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'DISCHARGE PHASE CHANGE MATERIAL MEMORY' [patent_app_type] => utility [patent_app_number] => 12/650676 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165726.pdf [firstpage_image] =>[orig_patent_app_number] => 12650676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8318558 [patent_doc_number] => 08233348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Bank active signal generation circuit' [patent_app_type] => utility [patent_app_number] => 12/648774 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3493 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8365127 [patent_doc_number] => 08254199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Multi-channel memory and power supply-driven channel selection' [patent_app_type] => utility [patent_app_number] => 12/648762 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5234 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6194595 [patent_doc_number] => 20110026349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'CIRCUIT FOR COMPENSATING TEMPERATURE DETECTION RANGE OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/649016 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3410 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20110026349.pdf [firstpage_image] =>[orig_patent_app_number] => 12649016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6078227 [patent_doc_number] => 20110141830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/648574 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3741 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20110141830.pdf [firstpage_image] =>[orig_patent_app_number] => 12648574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8423182 [patent_doc_number] => 08279673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/640848 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4662 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12640848 [rel_patent_id] =>[rel_patent_doc_number] =>)