Search

Pamela E. Perkins

Examiner (ID: 12468, Phone: (571)272-1840 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
888
Issued Applications
738
Pending Applications
17
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5452795 [patent_doc_number] => 20090068832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'THIN FILMS' [patent_app_type] => utility [patent_app_number] => 12/202132 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18943 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068832.pdf [firstpage_image] =>[orig_patent_app_number] => 12202132 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202132
Thin films Aug 28, 2008 Issued
Array ( [id] => 4836921 [patent_doc_number] => 20080277789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'DAMASCENE STRUCTURE AND OPENING THEREOF' [patent_app_type] => utility [patent_app_number] => 12/132604 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20080277789.pdf [firstpage_image] =>[orig_patent_app_number] => 12132604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132604
DAMASCENE STRUCTURE AND OPENING THEREOF Jun 2, 2008 Abandoned
Array ( [id] => 4727368 [patent_doc_number] => 20080206912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND METHOD OF CRYSTALLIZING SILICON' [patent_app_type] => utility [patent_app_number] => 12/110678 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5062 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206912.pdf [firstpage_image] =>[orig_patent_app_number] => 12110678 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110678
Array substrate, method of manufacturing the same and method of crystallizing silicon Apr 27, 2008 Issued
Array ( [id] => 4813434 [patent_doc_number] => 20080194065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'INTEGRATED CIRCUIT DEVICES HAVING AN EPITAXIAL PATTERN WITH A VOID REGION FORMED THEREIN AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/107468 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3954 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194065.pdf [firstpage_image] =>[orig_patent_app_number] => 12107468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107468
INTEGRATED CIRCUIT DEVICES HAVING AN EPITAXIAL PATTERN WITH A VOID REGION FORMED THEREIN AND METHODS OF FORMING THE SAME Apr 21, 2008 Abandoned
Array ( [id] => 4955020 [patent_doc_number] => 20080188044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'SEMICONDUCTOR DEVICES WITH DUAL-METAL GATE STRUCTURES AND FABRICATION METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/099827 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2666 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20080188044.pdf [firstpage_image] =>[orig_patent_app_number] => 12099827 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099827
Semiconductor devices with dual-metal gate structures and fabrication methods thereof Apr 8, 2008 Issued
Array ( [id] => 4747911 [patent_doc_number] => 20080155981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Methods for Forming Thermotunnel Generators Having Closely-Spaced Electrodes' [patent_app_type] => utility [patent_app_number] => 12/048897 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3319 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155981.pdf [firstpage_image] =>[orig_patent_app_number] => 12048897 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048897
Methods for forming thermotunnel generators having closely-spaced electrodes Mar 13, 2008 Issued
Array ( [id] => 4925223 [patent_doc_number] => 20080164586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Thin semiconductor package having stackable lead frame and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/076044 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3268 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20080164586.pdf [firstpage_image] =>[orig_patent_app_number] => 12076044 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076044
Thin semiconductor package having stackable lead frame and method of manufacturing the same Mar 12, 2008 Issued
Array ( [id] => 4639484 [patent_doc_number] => 08017511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/045438 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 3879 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/017/08017511.pdf [firstpage_image] =>[orig_patent_app_number] => 12045438 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045438
Method of manufacturing semiconductor device Mar 9, 2008 Issued
Array ( [id] => 252573 [patent_doc_number] => 07579206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Anchors for microelectromechanical systems having an SOI substrate, and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 12/008054 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 43 [patent_no_of_words] => 8895 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579206.pdf [firstpage_image] =>[orig_patent_app_number] => 12008054 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/008054
Anchors for microelectromechanical systems having an SOI substrate, and method of fabricating same Jan 6, 2008 Issued
Array ( [id] => 4474682 [patent_doc_number] => 07867872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Method for manufacturing semiconductor device with uniform concentration ion doping in recess gate channel region' [patent_app_type] => utility [patent_app_number] => 11/968758 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2221 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/867/07867872.pdf [firstpage_image] =>[orig_patent_app_number] => 11968758 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968758
Method for manufacturing semiconductor device with uniform concentration ion doping in recess gate channel region Jan 2, 2008 Issued
Array ( [id] => 8469748 [patent_doc_number] => 08298926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Silicon wafer with controlled distribution of embryos that become oxygen precipitates by succeeding annealing and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/521268 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5668 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12521268 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/521268
Silicon wafer with controlled distribution of embryos that become oxygen precipitates by succeeding annealing and its manufacturing method Dec 26, 2007 Issued
Array ( [id] => 6507422 [patent_doc_number] => 20100219459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'METHOD FOR MANUFACTURING A NON-VOLATILE MEMORY, NON-VOLATILE MEMORY DEVICE, AND AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/738409 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219459.pdf [firstpage_image] =>[orig_patent_app_number] => 12738409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/738409
Method for manufacturing a non-volatile memory, non-volatile memory device, and an integrated circuit Oct 22, 2007 Issued
Array ( [id] => 4528942 [patent_doc_number] => 07923365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon' [patent_app_type] => utility [patent_app_number] => 11/874118 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3258 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923365.pdf [firstpage_image] =>[orig_patent_app_number] => 11874118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874118
Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon Oct 16, 2007 Issued
Array ( [id] => 4765203 [patent_doc_number] => 20080176414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'SYSTEMS AND METHODS FOR INDUCING CRYSTALLIZATION OF THIN FILMS USING MULTIPLE OPTICAL PATHS' [patent_app_type] => utility [patent_app_number] => 11/873038 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8691 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20080176414.pdf [firstpage_image] =>[orig_patent_app_number] => 11873038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873038
Systems and methods for inducing crystallization of thin films using multiple optical paths Oct 15, 2007 Issued
Array ( [id] => 5285053 [patent_doc_number] => 20090098728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME' [patent_app_type] => utility [patent_app_number] => 11/870649 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1834 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20090098728.pdf [firstpage_image] =>[orig_patent_app_number] => 11870649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/870649
STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME Oct 10, 2007 Abandoned
Array ( [id] => 7740423 [patent_doc_number] => 08105960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Self-assembled sidewall spacer' [patent_app_type] => utility [patent_app_number] => 11/869178 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 7146 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/105/08105960.pdf [firstpage_image] =>[orig_patent_app_number] => 11869178 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869178
Self-assembled sidewall spacer Oct 8, 2007 Issued
Array ( [id] => 4451172 [patent_doc_number] => 07964495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Method of manufacturing complementary metal oxide semiconductor image sensor' [patent_app_type] => utility [patent_app_number] => 11/869498 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1399 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964495.pdf [firstpage_image] =>[orig_patent_app_number] => 11869498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869498
Method of manufacturing complementary metal oxide semiconductor image sensor Oct 8, 2007 Issued
Array ( [id] => 4909739 [patent_doc_number] => 20080020505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS' [patent_app_type] => utility [patent_app_number] => 11/863087 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5735 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20080020505.pdf [firstpage_image] =>[orig_patent_app_number] => 11863087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863087
Packaged microelectronic imagers and methods of packaging microelectronic imagers Sep 26, 2007 Issued
Array ( [id] => 7702940 [patent_doc_number] => 08088694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Method for forming a multiple layer passivation film and a device incorporating the same' [patent_app_type] => utility [patent_app_number] => 11/857288 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/088/08088694.pdf [firstpage_image] =>[orig_patent_app_number] => 11857288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/857288
Method for forming a multiple layer passivation film and a device incorporating the same Sep 17, 2007 Issued
Array ( [id] => 5452761 [patent_doc_number] => 20090068798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'IMAGER DIE PACKAGE AND METHODS OF PACKAGING AN IMAGER DIE ON A TEMPORARY CARRIER' [patent_app_type] => utility [patent_app_number] => 11/851787 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4863 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068798.pdf [firstpage_image] =>[orig_patent_app_number] => 11851787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851787
Imager die package and methods of packaging an imager die on a temporary carrier Sep 6, 2007 Issued
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