Pamela E. Perkins

Array ( [id] => 4443773 [patent_doc_number] => 07928571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Device having dual etch stop liner and reformed silicide layer and related methods' [patent_app_type] => utility [patent_app_number] => 11/850968 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1761 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/928/07928571.pdf [firstpage_image] =>[orig_patent_app_number] => 11850968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4768805 [patent_doc_number] => 20080054461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'RELIABLE WAFER-LEVEL CHIP-SCALE PACKAGE SOLDER BUMP STRUCTURE IN A PACKAGED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/847512 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2840 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054461.pdf [firstpage_image] =>[orig_patent_app_number] => 11847512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7515797 [patent_doc_number] => 08039869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Gallium nitride device substrate containing a lattice parameter altering element' [patent_app_type] => utility [patent_app_number] => 11/838467 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3726 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/039/08039869.pdf [firstpage_image] =>[orig_patent_app_number] => 11838467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3992 [patent_doc_number] => 07816156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Light emitting diode package and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/882167 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4388 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816156.pdf [firstpage_image] =>[orig_patent_app_number] => 11882167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 33252 [patent_doc_number] => 07785999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Formation of fully silicided metal gate using dual self-aligned silicide process' [patent_app_type] => utility [patent_app_number] => 11/830277 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5977 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/785/07785999.pdf [firstpage_image] =>[orig_patent_app_number] => 11830277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4624716 [patent_doc_number] => 08004017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Buried circumferential electrode microcavity plasma device arrays, electrical interconnects, and formation method' [patent_app_type] => utility [patent_app_number] => 11/880698 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8116 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004017.pdf [firstpage_image] =>[orig_patent_app_number] => 11880698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8029243 [patent_doc_number] => 08143706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Method of forming a component having dielectric sub-layers' [patent_app_type] => utility [patent_app_number] => 11/778201 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7289 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143706.pdf [firstpage_image] =>[orig_patent_app_number] => 11778201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4657704 [patent_doc_number] => 20080026565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Method of manufacturing a composite of copper and resin' [patent_app_type] => utility [patent_app_number] => 11/827687 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3004 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026565.pdf [firstpage_image] =>[orig_patent_app_number] => 11827687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4612992 [patent_doc_number] => 07989345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Methods of forming blind wafer interconnects, and related structures and assemblies' [patent_app_type] => utility [patent_app_number] => 11/776137 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 11283 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989345.pdf [firstpage_image] =>[orig_patent_app_number] => 11776137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7751396 [patent_doc_number] => 08110442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/819027 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 15118 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110442.pdf [firstpage_image] =>[orig_patent_app_number] => 11819027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8920813 [patent_doc_number] => 08486745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Multi-terminal phase change devices' [patent_app_type] => utility [patent_app_number] => 11/811077 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 56 [patent_no_of_words] => 5803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11811077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 82835 [patent_doc_number] => 07745904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Shallow trench isolation structure for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/809519 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2950 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/745/07745904.pdf [firstpage_image] =>[orig_patent_app_number] => 11809519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4583277 [patent_doc_number] => 07851381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Surface treatment method for nitride crystal, nitride crystal substrate, nitride crystal substrate with epitaxial layer and semiconductor device, and method of manufacturing nitride crystal substrate with epitaxial layer and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/806317 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 13817 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851381.pdf [firstpage_image] =>[orig_patent_app_number] => 11806317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4792230 [patent_doc_number] => 20080293204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Shallow junction formation and high dopant activation rate of MOS devices' [patent_app_type] => utility [patent_app_number] => 11/804927 [patent_app_country] => US [patent_app_date] => 2007-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2360 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20080293204.pdf [firstpage_image] =>[orig_patent_app_number] => 11804927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7597676 [patent_doc_number] => 07618901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3' [patent_app_type] => utility [patent_app_number] => 11/744458 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1820 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/618/07618901.pdf [firstpage_image] =>[orig_patent_app_number] => 11744458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7503307 [patent_doc_number] => 08034683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Method of forming a phase change material layer, method of forming a phase change memory device using the same, and a phase change memory device so formed' [patent_app_type] => utility [patent_app_number] => 11/785807 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/034/08034683.pdf [firstpage_image] =>[orig_patent_app_number] => 11785807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5098671 [patent_doc_number] => 20070181931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'HAFNIUM TANTALUM OXIDE DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 11/735247 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10286 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20070181931.pdf [firstpage_image] =>[orig_patent_app_number] => 11735247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8164350 [patent_doc_number] => 08173537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-08 [patent_title] => 'Methods for reducing UV and dielectric diffusion barrier interaction' [patent_app_type] => utility [patent_app_number] => 11/693617 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9555 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/173/08173537.pdf [firstpage_image] =>[orig_patent_app_number] => 11693617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4495680 [patent_doc_number] => 07947565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Forming method of porous low-k layer and interconnect process' [patent_app_type] => utility [patent_app_number] => 11/672307 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4499 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/947/07947565.pdf [firstpage_image] =>[orig_patent_app_number] => 11672307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5236613 [patent_doc_number] => 20070128770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'MICROELECTRONIC COMPONENT ASSEMBLIES HAVING LEAD FRAMES ADAPTED TO REDUCE PACKAGE BOW' [patent_app_type] => utility [patent_app_number] => 11/672297 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7559 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128770.pdf [firstpage_image] =>[orig_patent_app_number] => 11672297 [rel_patent_id] =>[rel_patent_doc_number] =>)