Search

Pamela E. Perkins

Examiner (ID: 12468, Phone: (571)272-1840 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
888
Issued Applications
738
Pending Applications
17
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 327002 [patent_doc_number] => 07514776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Semiconductor/printed circuit board assembly, and computer system' [patent_app_type] => utility [patent_app_number] => 11/668127 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3878 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514776.pdf [firstpage_image] =>[orig_patent_app_number] => 11668127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668127
Semiconductor/printed circuit board assembly, and computer system Jan 28, 2007 Issued
Array ( [id] => 4846019 [patent_doc_number] => 20080182427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Deposition method for transition-metal oxide based dielectric' [patent_app_type] => utility [patent_app_number] => 11/698337 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4028 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182427.pdf [firstpage_image] =>[orig_patent_app_number] => 11698337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698337
Deposition method for transition-metal oxide based dielectric Jan 25, 2007 Abandoned
Array ( [id] => 4762818 [patent_doc_number] => 20080174027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'SEMICONDUCTOR INTERCONNECT STRUCTURE WITH ROUNDED EDGES AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/625527 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20080174027.pdf [firstpage_image] =>[orig_patent_app_number] => 11625527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625527
SEMICONDUCTOR INTERCONNECT STRUCTURE WITH ROUNDED EDGES AND METHOD FOR FORMING THE SAME Jan 21, 2007 Abandoned
Array ( [id] => 5098623 [patent_doc_number] => 20070181883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Semiconductor device having a modified dielectric film' [patent_app_type] => utility [patent_app_number] => 11/655227 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6953 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20070181883.pdf [firstpage_image] =>[orig_patent_app_number] => 11655227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655227
Semiconductor device having a modified dielectric film Jan 18, 2007 Issued
Array ( [id] => 4558471 [patent_doc_number] => 07838444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Semiconductor device and fabrication method of the same' [patent_app_type] => utility [patent_app_number] => 11/654497 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4387 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838444.pdf [firstpage_image] =>[orig_patent_app_number] => 11654497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654497
Semiconductor device and fabrication method of the same Jan 17, 2007 Issued
Array ( [id] => 4971459 [patent_doc_number] => 20070111461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Systems And Methods For Forming Integrated Circuit Components Having Matching Geometries' [patent_app_type] => utility [patent_app_number] => 11/622735 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5811 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111461.pdf [firstpage_image] =>[orig_patent_app_number] => 11622735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/622735
Systems And Methods For Forming Integrated Circuit Components Having Matching Geometries Jan 11, 2007 Abandoned
Array ( [id] => 5095753 [patent_doc_number] => 20070117362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Heat treatment apparatus and method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/652094 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6716 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117362.pdf [firstpage_image] =>[orig_patent_app_number] => 11652094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652094
Heat treatment apparatus and method of manufacturing a semiconductor device Jan 10, 2007 Issued
Array ( [id] => 232696 [patent_doc_number] => 07598121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/648646 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7144 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598121.pdf [firstpage_image] =>[orig_patent_app_number] => 11648646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648646
Method of manufacturing a semiconductor device Jan 2, 2007 Issued
Array ( [id] => 4571288 [patent_doc_number] => 07829422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Integrated circuit having ultralow-K dielectric layer' [patent_app_type] => utility [patent_app_number] => 11/615007 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3250 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/829/07829422.pdf [firstpage_image] =>[orig_patent_app_number] => 11615007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615007
Integrated circuit having ultralow-K dielectric layer Dec 21, 2006 Issued
Array ( [id] => 4523341 [patent_doc_number] => 07951699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/637097 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 95 [patent_no_of_words] => 13750 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/951/07951699.pdf [firstpage_image] =>[orig_patent_app_number] => 11637097 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637097
Method of manufacturing semiconductor device Dec 11, 2006 Issued
Array ( [id] => 4533921 [patent_doc_number] => 07888272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Methods for manufacturing memory and logic devices using the same process without the need for additional masks' [patent_app_type] => utility [patent_app_number] => 11/609747 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 3898 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888272.pdf [firstpage_image] =>[orig_patent_app_number] => 11609747 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609747
Methods for manufacturing memory and logic devices using the same process without the need for additional masks Dec 11, 2006 Issued
Array ( [id] => 311020 [patent_doc_number] => 07528044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'CMOSFET with hybrid-strained channels' [patent_app_type] => utility [patent_app_number] => 11/562522 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3745 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528044.pdf [firstpage_image] =>[orig_patent_app_number] => 11562522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562522
CMOSFET with hybrid-strained channels Nov 21, 2006 Issued
Array ( [id] => 112363 [patent_doc_number] => 07713829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology' [patent_app_type] => utility [patent_app_number] => 11/562735 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3067 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/713/07713829.pdf [firstpage_image] =>[orig_patent_app_number] => 11562735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562735
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology Nov 21, 2006 Issued
Array ( [id] => 8351921 [patent_doc_number] => 08247250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Method for manufacturing liquid crystal display device' [patent_app_type] => utility [patent_app_number] => 11/602997 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 9147 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11602997 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602997
Method for manufacturing liquid crystal display device Nov 21, 2006 Issued
Array ( [id] => 4899422 [patent_doc_number] => 20080119036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'WIRE AND SOLDER BOND FORMING METHODS' [patent_app_type] => utility [patent_app_number] => 11/561437 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20080119036.pdf [firstpage_image] =>[orig_patent_app_number] => 11561437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561437
Wire and solder bond forming methods Nov 19, 2006 Issued
Array ( [id] => 4692821 [patent_doc_number] => 20080085592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/600057 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3889 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085592.pdf [firstpage_image] =>[orig_patent_app_number] => 11600057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600057
Method for manufacturing semiconductor device Nov 15, 2006 Issued
Array ( [id] => 5171886 [patent_doc_number] => 20070072319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'INTEGRATED CIRCUIT CAPACITOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/559317 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6034 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072319.pdf [firstpage_image] =>[orig_patent_app_number] => 11559317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559317
INTEGRATED CIRCUIT CAPACITOR STRUCTURE Nov 12, 2006 Abandoned
Array ( [id] => 5069706 [patent_doc_number] => 20070190808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'LOW-K DIELECTRIC LAYERS FOR LARGE SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/558217 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5138 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190808.pdf [firstpage_image] =>[orig_patent_app_number] => 11558217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/558217
LOW-K DIELECTRIC LAYERS FOR LARGE SUBSTRATES Nov 8, 2006 Abandoned
Array ( [id] => 5056940 [patent_doc_number] => 20070059862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Multiple chip semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/595067 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4153 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059862.pdf [firstpage_image] =>[orig_patent_app_number] => 11595067 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/595067
Multiple chip semiconductor package Nov 8, 2006 Issued
Array ( [id] => 4965361 [patent_doc_number] => 20080108181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'METHOD FOR ATTACHING INTEGRATED CIRCUIT COMPONENT TO A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/556887 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2685 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108181.pdf [firstpage_image] =>[orig_patent_app_number] => 11556887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556887
METHOD FOR ATTACHING INTEGRATED CIRCUIT COMPONENT TO A SUBSTRATE Nov 5, 2006 Abandoned
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