
Pamela E. Perkins
Examiner (ID: 12468, Phone: (571)272-1840 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 888 |
| Issued Applications | 738 |
| Pending Applications | 17 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 327002
[patent_doc_number] => 07514776
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-07
[patent_title] => 'Semiconductor/printed circuit board assembly, and computer system'
[patent_app_type] => utility
[patent_app_number] => 11/668127
[patent_app_country] => US
[patent_app_date] => 2007-01-29
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[pdf_file] => patents/07/514/07514776.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/668127 | Semiconductor/printed circuit board assembly, and computer system | Jan 28, 2007 | Issued |
Array
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[id] => 4846019
[patent_doc_number] => 20080182427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Deposition method for transition-metal oxide based dielectric'
[patent_app_type] => utility
[patent_app_number] => 11/698337
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/698337 | Deposition method for transition-metal oxide based dielectric | Jan 25, 2007 | Abandoned |
Array
(
[id] => 4762818
[patent_doc_number] => 20080174027
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[patent_issue_date] => 2008-07-24
[patent_title] => 'SEMICONDUCTOR INTERCONNECT STRUCTURE WITH ROUNDED EDGES AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/625527
[patent_app_country] => US
[patent_app_date] => 2007-01-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/625527 | SEMICONDUCTOR INTERCONNECT STRUCTURE WITH ROUNDED EDGES AND METHOD FOR FORMING THE SAME | Jan 21, 2007 | Abandoned |
Array
(
[id] => 5098623
[patent_doc_number] => 20070181883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Semiconductor device having a modified dielectric film'
[patent_app_type] => utility
[patent_app_number] => 11/655227
[patent_app_country] => US
[patent_app_date] => 2007-01-19
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Array
(
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[patent_issue_date] => 2010-11-23
[patent_title] => 'Semiconductor device and fabrication method of the same'
[patent_app_type] => utility
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Array
(
[id] => 4971459
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[patent_title] => 'Systems And Methods For Forming Integrated Circuit Components Having Matching Geometries'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/622735 | Systems And Methods For Forming Integrated Circuit Components Having Matching Geometries | Jan 11, 2007 | Abandoned |
Array
(
[id] => 5095753
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[patent_title] => 'Heat treatment apparatus and method of manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/652094
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/652094 | Heat treatment apparatus and method of manufacturing a semiconductor device | Jan 10, 2007 | Issued |
Array
(
[id] => 232696
[patent_doc_number] => 07598121
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[patent_kind] => B2
[patent_issue_date] => 2009-10-06
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/648646
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648646 | Method of manufacturing a semiconductor device | Jan 2, 2007 | Issued |
Array
(
[id] => 4571288
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[patent_title] => 'Integrated circuit having ultralow-K dielectric layer'
[patent_app_type] => utility
[patent_app_number] => 11/615007
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[firstpage_image] =>[orig_patent_app_number] => 11615007
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615007 | Integrated circuit having ultralow-K dielectric layer | Dec 21, 2006 | Issued |
Array
(
[id] => 4523341
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[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/637097 | Method of manufacturing semiconductor device | Dec 11, 2006 | Issued |
Array
(
[id] => 4533921
[patent_doc_number] => 07888272
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[patent_title] => 'Methods for manufacturing memory and logic devices using the same process without the need for additional masks'
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Array
(
[id] => 311020
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/562522 | CMOSFET with hybrid-strained channels | Nov 21, 2006 | Issued |
Array
(
[id] => 112363
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[patent_title] => 'Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology'
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Array
(
[id] => 8351921
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[patent_title] => 'Method for manufacturing liquid crystal display device'
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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