Pamela E. Perkins

Array ( [id] => 4138 [patent_doc_number] => 07816231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Device structures including backside contacts, and methods for forming same' [patent_app_type] => utility [patent_app_number] => 11/468068 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5517 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816231.pdf [firstpage_image] =>[orig_patent_app_number] => 11468068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5602397 [patent_doc_number] => 20060292742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Manufacturing method for packaged semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/511267 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4127 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292742.pdf [firstpage_image] =>[orig_patent_app_number] => 11511267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5602368 [patent_doc_number] => 20060292713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/511417 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2047 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292713.pdf [firstpage_image] =>[orig_patent_app_number] => 11511417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4999978 [patent_doc_number] => 20070042612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/507007 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042612.pdf [firstpage_image] =>[orig_patent_app_number] => 11507007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4669907 [patent_doc_number] => 20080044967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'INTEGRATED CIRCUIT SYSTEM HAVING STRAINED TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/465799 [patent_app_country] => US [patent_app_date] => 2006-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044967.pdf [firstpage_image] =>[orig_patent_app_number] => 11465799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 63846 [patent_doc_number] => 07759260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Selective nitridation of gate oxides' [patent_app_type] => utility [patent_app_number] => 11/465030 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4643 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759260.pdf [firstpage_image] =>[orig_patent_app_number] => 11465030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5889203 [patent_doc_number] => 20060276019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Method for production of contacts on a wafer' [patent_app_type] => utility [patent_app_number] => 11/503557 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20060276019.pdf [firstpage_image] =>[orig_patent_app_number] => 11503557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5145798 [patent_doc_number] => 20070045852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'METHOD OF MANUFACTURING AN INSULATING LAYER AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 11/463287 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045852.pdf [firstpage_image] =>[orig_patent_app_number] => 11463287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5608692 [patent_doc_number] => 20060270208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Methods of making semiconductor fuses' [patent_app_type] => utility [patent_app_number] => 11/499134 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4222 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20060270208.pdf [firstpage_image] =>[orig_patent_app_number] => 11499134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5625512 [patent_doc_number] => 20060264017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/495663 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2816 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20060264017.pdf [firstpage_image] =>[orig_patent_app_number] => 11495663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 303554 [patent_doc_number] => 07534691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Isolation structures for preventing photons and carriers from reaching active areas and methods of formation' [patent_app_type] => utility [patent_app_number] => 11/495547 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4879 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534691.pdf [firstpage_image] =>[orig_patent_app_number] => 11495547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5136046 [patent_doc_number] => 20070077675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'ELECTRONIC COMPONENT PACKAGING' [patent_app_type] => utility [patent_app_number] => 11/459187 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20070077675.pdf [firstpage_image] =>[orig_patent_app_number] => 11459187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5661681 [patent_doc_number] => 20060252277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Methods of forming patterned photoresist layers over semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 11/481493 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2939 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20060252277.pdf [firstpage_image] =>[orig_patent_app_number] => 11481493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5834792 [patent_doc_number] => 20060246623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/477550 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5356 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20060246623.pdf [firstpage_image] =>[orig_patent_app_number] => 11477550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 363446 [patent_doc_number] => 07482257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method for forming metal contact in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/479287 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2883 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482257.pdf [firstpage_image] =>[orig_patent_app_number] => 11479287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5832275 [patent_doc_number] => 20060244105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Strained semiconductor by full wafer bonding' [patent_app_type] => utility [patent_app_number] => 11/475798 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10170 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20060244105.pdf [firstpage_image] =>[orig_patent_app_number] => 11475798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5199286 [patent_doc_number] => 20070298604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD FOR FABRICATING SINGLE-DAMASCENE STRUCTURE, DUAL DAMASCENE STRUCTURE, AND OPENING THEREOF' [patent_app_type] => utility [patent_app_number] => 11/309097 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4043 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298604.pdf [firstpage_image] =>[orig_patent_app_number] => 11309097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5688459 [patent_doc_number] => 20060286774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'METHOD FOR FORMING SILICON-CONTAINING MATERIALS DURING A PHOTOEXCITATION DEPOSITION PROCESS' [patent_app_type] => utility [patent_app_number] => 11/425342 [patent_app_country] => US [patent_app_date] => 2006-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 28690 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286774.pdf [firstpage_image] =>[orig_patent_app_number] => 11425342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5922930 [patent_doc_number] => 20060240652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'VERY LOW DIELECTRIC CONSTANT PLASMA-ENHANCED CVD FILMS' [patent_app_type] => utility [patent_app_number] => 11/424719 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10040 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20060240652.pdf [firstpage_image] =>[orig_patent_app_number] => 11424719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 62822 [patent_doc_number] => 07763536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/424167 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3415 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763536.pdf [firstpage_image] =>[orig_patent_app_number] => 11424167 [rel_patent_id] =>[rel_patent_doc_number] =>)