Search

Pamela E. Perkins

Examiner (ID: 9478, Phone: (571)272-1840 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
888
Issued Applications
738
Pending Applications
17
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 530485 [patent_doc_number] => 07183637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Microelectronic mechanical system and methods' [patent_app_type] => utility [patent_app_number] => 11/129541 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7455 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183637.pdf [firstpage_image] =>[orig_patent_app_number] => 11129541 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129541
Microelectronic mechanical system and methods May 12, 2005 Issued
Array ( [id] => 432632 [patent_doc_number] => 07265406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Capacitor with conducting nanostructure' [patent_app_type] => utility [patent_app_number] => 11/125567 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5385 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265406.pdf [firstpage_image] =>[orig_patent_app_number] => 11125567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/125567
Capacitor with conducting nanostructure May 8, 2005 Issued
Array ( [id] => 7053522 [patent_doc_number] => 20050274693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Device and method for lithography' [patent_app_type] => utility [patent_app_number] => 11/123087 [patent_app_country] => US [patent_app_date] => 2005-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7597 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20050274693.pdf [firstpage_image] =>[orig_patent_app_number] => 11123087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/123087
Device and method for lithography May 5, 2005 Abandoned
Array ( [id] => 7019553 [patent_doc_number] => 20050221572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature' [patent_app_type] => utility [patent_app_number] => 11/124247 [patent_app_country] => US [patent_app_date] => 2005-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7805 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221572.pdf [firstpage_image] =>[orig_patent_app_number] => 11124247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/124247
High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature May 5, 2005 Issued
Array ( [id] => 5765768 [patent_doc_number] => 20050263831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Hybrid planar and FinFET CMOS devices' [patent_app_type] => utility [patent_app_number] => 11/122193 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4814 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263831.pdf [firstpage_image] =>[orig_patent_app_number] => 11122193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/122193
Hybrid planar and FinFET CMOS devices May 3, 2005 Issued
Array ( [id] => 432292 [patent_doc_number] => 07265065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Method for fabricating dielectric layer doped with nitrogen' [patent_app_type] => utility [patent_app_number] => 10/908157 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1850 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265065.pdf [firstpage_image] =>[orig_patent_app_number] => 10908157 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908157
Method for fabricating dielectric layer doped with nitrogen Apr 28, 2005 Issued
Array ( [id] => 879787 [patent_doc_number] => 07354826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-08 [patent_title] => 'Method for forming memory array bitlines comprising epitaxially grown silicon and related structure' [patent_app_type] => utility [patent_app_number] => 11/112607 [patent_app_country] => US [patent_app_date] => 2005-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3625 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/354/07354826.pdf [firstpage_image] =>[orig_patent_app_number] => 11112607 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/112607
Method for forming memory array bitlines comprising epitaxially grown silicon and related structure Apr 21, 2005 Issued
Array ( [id] => 5851327 [patent_doc_number] => 20060234518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Chemical Vapor Deposition Method Preventing Particles Forming in Chamber' [patent_app_type] => utility [patent_app_number] => 10/907857 [patent_app_country] => US [patent_app_date] => 2005-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20060234518.pdf [firstpage_image] =>[orig_patent_app_number] => 10907857 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907857
Chemical vapor deposition method preventing particles forming in chamber Apr 17, 2005 Issued
Array ( [id] => 7136933 [patent_doc_number] => 20050181598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films' [patent_app_type] => utility [patent_app_number] => 11/105597 [patent_app_country] => US [patent_app_date] => 2005-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5300 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181598.pdf [firstpage_image] =>[orig_patent_app_number] => 11105597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/105597
Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films Apr 14, 2005 Issued
Array ( [id] => 7136870 [patent_doc_number] => 20050181555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Thin films' [patent_app_type] => utility [patent_app_number] => 11/106220 [patent_app_country] => US [patent_app_date] => 2005-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18932 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181555.pdf [firstpage_image] =>[orig_patent_app_number] => 11106220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/106220
Thin films Apr 12, 2005 Issued
Array ( [id] => 6912463 [patent_doc_number] => 20050176221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Plasma CVD apparatus' [patent_app_type] => utility [patent_app_number] => 11/102727 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5033 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176221.pdf [firstpage_image] =>[orig_patent_app_number] => 11102727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/102727
Plasma CVD apparatus Apr 10, 2005 Issued
Array ( [id] => 6912455 [patent_doc_number] => 20050176213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Hemi-spherical grain silicon enhancement' [patent_app_type] => utility [patent_app_number] => 11/097857 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3663 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176213.pdf [firstpage_image] =>[orig_patent_app_number] => 11097857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097857
Hemi-spherical grain silicon enhancement Mar 30, 2005 Abandoned
Array ( [id] => 5859022 [patent_doc_number] => 20060228832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Leadframe semiconductor package stand and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/094557 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20060228832.pdf [firstpage_image] =>[orig_patent_app_number] => 11094557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/094557
Leadframe semiconductor package stand and method for making the same Mar 30, 2005 Issued
Array ( [id] => 6966663 [patent_doc_number] => 20050233560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Silicon substrates with multi-grooved surface and production methods thereof' [patent_app_type] => utility [patent_app_number] => 11/084083 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3338 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233560.pdf [firstpage_image] =>[orig_patent_app_number] => 11084083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/084083
Silicon substrates with multi-grooved surface and production methods thereof Mar 16, 2005 Abandoned
Array ( [id] => 795590 [patent_doc_number] => 07429504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-30 [patent_title] => 'Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods' [patent_app_type] => utility [patent_app_number] => 11/080737 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5724 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/429/07429504.pdf [firstpage_image] =>[orig_patent_app_number] => 11080737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080737
Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods Mar 14, 2005 Issued
Array ( [id] => 6983499 [patent_doc_number] => 20050153569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3' [patent_app_type] => utility [patent_app_number] => 11/075187 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1764 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153569.pdf [firstpage_image] =>[orig_patent_app_number] => 11075187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/075187
Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 Mar 7, 2005 Issued
Array ( [id] => 5750874 [patent_doc_number] => 20060220023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Thin-film device' [patent_app_type] => utility [patent_app_number] => 11/072947 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6424 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220023.pdf [firstpage_image] =>[orig_patent_app_number] => 11072947 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/072947
Thin-film device Mar 2, 2005 Abandoned
Array ( [id] => 62881 [patent_doc_number] => 07763550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Method of forming a layer on a wafer' [patent_app_type] => utility [patent_app_number] => 11/061407 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3498 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763550.pdf [firstpage_image] =>[orig_patent_app_number] => 11061407 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061407
Method of forming a layer on a wafer Feb 17, 2005 Issued
Array ( [id] => 442911 [patent_doc_number] => 07256143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Semiconductor device having self-aligned contact plug and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/058670 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6059 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256143.pdf [firstpage_image] =>[orig_patent_app_number] => 11058670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058670
Semiconductor device having self-aligned contact plug and method for fabricating the same Feb 14, 2005 Issued
Array ( [id] => 7111300 [patent_doc_number] => 20050208756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Method of removing resist, semiconductor device thereby and method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/052987 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5679 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208756.pdf [firstpage_image] =>[orig_patent_app_number] => 11052987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/052987
Method of removing resist, semiconductor device thereby and method of manufacturing a semiconductor device Feb 8, 2005 Issued
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