Search

Pamela E. Perkins

Examiner (ID: 9478, Phone: (571)272-1840 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
888
Issued Applications
738
Pending Applications
17
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 868220 [patent_doc_number] => 07364999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Method for interconnecting semiconductor components with substrates and contact means' [patent_app_type] => utility [patent_app_number] => 11/051257 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1813 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/364/07364999.pdf [firstpage_image] =>[orig_patent_app_number] => 11051257 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051257
Method for interconnecting semiconductor components with substrates and contact means Feb 3, 2005 Issued
Array ( [id] => 404608 [patent_doc_number] => 07288437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Conductive pattern producing method and its applications' [patent_app_type] => utility [patent_app_number] => 11/048767 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 1323 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288437.pdf [firstpage_image] =>[orig_patent_app_number] => 11048767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048767
Conductive pattern producing method and its applications Feb 2, 2005 Issued
Array ( [id] => 7050840 [patent_doc_number] => 20050186727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Simplified bottom electrode-barrier structure for making a ferroelectric capacitor stacked on a contact plug' [patent_app_type] => utility [patent_app_number] => 11/046057 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7245 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186727.pdf [firstpage_image] =>[orig_patent_app_number] => 11046057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046057
Simplified bottom electrode-barrier structure for making a ferroelectric capacitor stacked on a contact plug Jan 27, 2005 Issued
Array ( [id] => 672074 [patent_doc_number] => 07091084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Ultra-high capacitance device based on nanostructures' [patent_app_type] => utility [patent_app_number] => 11/044114 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5362 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091084.pdf [firstpage_image] =>[orig_patent_app_number] => 11044114 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044114
Ultra-high capacitance device based on nanostructures Jan 25, 2005 Issued
Array ( [id] => 5874479 [patent_doc_number] => 20060166398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Off-grid decoupling of ball grid array (BGA) devices and method' [patent_app_type] => utility [patent_app_number] => 11/041727 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2021 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166398.pdf [firstpage_image] =>[orig_patent_app_number] => 11041727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041727
Off-grid decoupling of ball grid array (BGA) devices and method Jan 24, 2005 Issued
Array ( [id] => 5874641 [patent_doc_number] => 20060166514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'TEOS deposition method' [patent_app_type] => utility [patent_app_number] => 11/040307 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2161 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166514.pdf [firstpage_image] =>[orig_patent_app_number] => 11040307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040307
TEOS deposition method Jan 20, 2005 Issued
Array ( [id] => 5874641 [patent_doc_number] => 20060166514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'TEOS deposition method' [patent_app_type] => utility [patent_app_number] => 11/040307 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2161 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166514.pdf [firstpage_image] =>[orig_patent_app_number] => 11040307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040307
TEOS deposition method Jan 20, 2005 Issued
Array ( [id] => 7169180 [patent_doc_number] => 20050121761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/035986 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 20550 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121761.pdf [firstpage_image] =>[orig_patent_app_number] => 11035986 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035986
Semiconductor device and method for fabricating the same Jan 17, 2005 Issued
Array ( [id] => 5631710 [patent_doc_number] => 20060148180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Atomic layer deposited hafnium tantalum oxide dielectrics' [patent_app_type] => utility [patent_app_number] => 11/029757 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10364 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148180.pdf [firstpage_image] =>[orig_patent_app_number] => 11029757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029757
Atomic layer deposited hafnium tantalum oxide dielectrics Jan 4, 2005 Issued
Array ( [id] => 7253827 [patent_doc_number] => 20050142862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Dual damascene interconnection in semiconductor device and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/024657 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2601 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142862.pdf [firstpage_image] =>[orig_patent_app_number] => 11024657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024657
Dual damascene interconnection in semiconductor device and method for forming the same Dec 29, 2004 Issued
Array ( [id] => 6983446 [patent_doc_number] => 20050153516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method for etching upper metal of capacitator' [patent_app_type] => utility [patent_app_number] => 11/024727 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1705 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153516.pdf [firstpage_image] =>[orig_patent_app_number] => 11024727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024727
Method for etching upper metal of capacitator Dec 29, 2004 Issued
Array ( [id] => 418767 [patent_doc_number] => 07276439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Method for forming contact hole for dual damascene interconnection in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/024847 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1704 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/276/07276439.pdf [firstpage_image] =>[orig_patent_app_number] => 11024847 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024847
Method for forming contact hole for dual damascene interconnection in semiconductor device Dec 29, 2004 Issued
Array ( [id] => 5655930 [patent_doc_number] => 20060141666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby' [patent_app_type] => utility [patent_app_number] => 11/024237 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2291 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141666.pdf [firstpage_image] =>[orig_patent_app_number] => 11024237 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024237
Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby Dec 28, 2004 Abandoned
Array ( [id] => 442851 [patent_doc_number] => 07256120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Method to eliminate plating copper defect' [patent_app_type] => utility [patent_app_number] => 11/024917 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2797 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256120.pdf [firstpage_image] =>[orig_patent_app_number] => 11024917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024917
Method to eliminate plating copper defect Dec 27, 2004 Issued
Array ( [id] => 860301 [patent_doc_number] => 07371653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Metal interconnection structure of semiconductor device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/019267 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2406 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/371/07371653.pdf [firstpage_image] =>[orig_patent_app_number] => 11019267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019267
Metal interconnection structure of semiconductor device and method of forming the same Dec 22, 2004 Issued
Array ( [id] => 7236874 [patent_doc_number] => 20050140023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/017077 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140023.pdf [firstpage_image] =>[orig_patent_app_number] => 11017077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017077
Method of manufacturing a semiconductor device Dec 20, 2004 Abandoned
Array ( [id] => 5649169 [patent_doc_number] => 20060134904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Microelecromechanical system microphone fabrication including signal processing circuitry on common substrate' [patent_app_type] => utility [patent_app_number] => 11/022457 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2941 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134904.pdf [firstpage_image] =>[orig_patent_app_number] => 11022457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022457
Microelectromechanical system microphone fabrication including signal processing circuitry on common substrate Dec 20, 2004 Issued
Array ( [id] => 797948 [patent_doc_number] => 07427535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Semiconductor/printed circuit board assembly, and computer system' [patent_app_type] => utility [patent_app_number] => 11/013487 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3819 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427535.pdf [firstpage_image] =>[orig_patent_app_number] => 11013487 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013487
Semiconductor/printed circuit board assembly, and computer system Dec 15, 2004 Issued
Array ( [id] => 5649094 [patent_doc_number] => 20060134829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Wafer scale integration of electroplate 3D structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding' [patent_app_type] => utility [patent_app_number] => 11/012597 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134829.pdf [firstpage_image] =>[orig_patent_app_number] => 11012597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012597
Wafer scale integration of electroplated 3D structures using successive lithography, electroplated sacrificial layers, and flip-chip bonding Dec 15, 2004 Issued
Array ( [id] => 584044 [patent_doc_number] => 07446062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Device having dual etch stop liner and reformed silicide layer and related methods' [patent_app_type] => utility [patent_app_number] => 10/905027 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1731 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446062.pdf [firstpage_image] =>[orig_patent_app_number] => 10905027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905027
Device having dual etch stop liner and reformed silicide layer and related methods Dec 9, 2004 Issued
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