Pamela E. Perkins

Array ( [id] => 10277201 [patent_doc_number] => 20150162198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A DOUBLE DEEP WELL AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/626259 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10277268 [patent_doc_number] => 20150162266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS' [patent_app_type] => utility [patent_app_number] => 14/618106 [patent_app_country] => US [patent_app_date] => 2015-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6246 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14618106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10583720 [patent_doc_number] => 09305846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Device isolation in FinFET CMOS' [patent_app_type] => utility [patent_app_number] => 14/599873 [patent_app_country] => US [patent_app_date] => 2015-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 4616 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14599873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11360128 [patent_doc_number] => 09536783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Wafer-level die attach metallization' [patent_app_type] => utility [patent_app_number] => 14/591566 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9176 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11286544 [patent_doc_number] => 09502404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Epitaxial formation mechanisms of source and drain regions' [patent_app_type] => utility [patent_app_number] => 14/549316 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9913401 [patent_doc_number] => 20150068604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'SPALLING METHODS TO FORM MULTI-JUNCTION PHOTOVOLTAIC STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/540315 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11667 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11411652 [patent_doc_number] => 09558964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Method of fabricating low CTE interposer without TSV structure' [patent_app_type] => utility [patent_app_number] => 14/524280 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4589 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10583811 [patent_doc_number] => 09305937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-05 [patent_title] => 'Bottom recess process for an outer blocking dielectric layer inside a memory opening' [patent_app_type] => utility [patent_app_number] => 14/519733 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 16203 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10463984 [patent_doc_number] => 20150348999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'Manufacturing Method of an Array Substrate' [patent_app_type] => utility [patent_app_number] => 14/519480 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6738 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765170 [patent_doc_number] => 20160111326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Early Bit Line Air Gap Formation' [patent_app_type] => utility [patent_app_number] => 14/520117 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8578 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10370495 [patent_doc_number] => 20150255501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SOLID STATE IMAGING DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/518495 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5913 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11346371 [patent_doc_number] => 09530787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Batch contacts for multiple electrically conductive layers' [patent_app_type] => utility [patent_app_number] => 14/518430 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 19704 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11279894 [patent_doc_number] => 09496379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Method and structure for III-V FinFET' [patent_app_type] => utility [patent_app_number] => 14/518281 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 6514 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11244901 [patent_doc_number] => 09470940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Semiconductor device and method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/517376 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 5462 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10453547 [patent_doc_number] => 20150338562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'POLARIZING FILTER AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/517296 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2282 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765456 [patent_doc_number] => 20160111612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'LIGHT EMITTING DIODE HAVING MIRROR PROTECTION LAYER AND METHOD FOR MANUFACTURING MIRROR PROTECTION LAYER' [patent_app_type] => utility [patent_app_number] => 14/517502 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2598 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10715530 [patent_doc_number] => 20160061677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'VARIOUS STRESS FREE SENSOR PACKAGES USING WAFER LEVEL SUPPORTING DIE AND AIR GAP TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 14/517387 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8812 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765386 [patent_doc_number] => 20160111541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'GATE LAST SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/517272 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4717 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9901596 [patent_doc_number] => 20150056796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS' [patent_app_type] => utility [patent_app_number] => 14/514422 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2479 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11585915 [patent_doc_number] => 09640566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Thin film transistor array panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/487300 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11472 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487300 [rel_patent_id] =>[rel_patent_doc_number] =>)