Search

Pamela E. Perkins

Examiner (ID: 8226, Phone: (571)272-1840 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
888
Issued Applications
738
Pending Applications
17
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9839084 [patent_doc_number] => 20150031165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'PHOTOVOLTAIC DEVICE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 14/483537 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3399 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483537 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483537
PHOTOVOLTAIC DEVICE INTERCONNECT Sep 10, 2014 Abandoned
Array ( [id] => 10244959 [patent_doc_number] => 20150129954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/474942 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 8640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14474942 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/474942
Semiconductor memory device and method of manufacturing the same Sep 1, 2014 Issued
Array ( [id] => 9938014 [patent_doc_number] => 08987826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/469013 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6537 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14469013 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/469013
Method of manufacturing semiconductor device Aug 25, 2014 Issued
Array ( [id] => 10710138 [patent_doc_number] => 20160056285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE WITH INCREASED CUTOFF FREQUENCY' [patent_app_type] => utility [patent_app_number] => 14/467054 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2937 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467054
HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE WITH INCREASED CUTOFF FREQUENCY Aug 24, 2014 Abandoned
Array ( [id] => 10709952 [patent_doc_number] => 20160056099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'INTEGRATED CIRCUIT WITH ON-DIE DECOUPLING CAPACITORS' [patent_app_type] => utility [patent_app_number] => 14/467039 [patent_app_country] => US [patent_app_date] => 2014-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2959 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467039
Integrated circuit with on-die decoupling capacitors Aug 23, 2014 Issued
Array ( [id] => 10479579 [patent_doc_number] => 20150364596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/467040 [patent_app_country] => US [patent_app_date] => 2014-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5418 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467040
Thin film transistor Aug 23, 2014 Issued
Array ( [id] => 10960922 [patent_doc_number] => 20140363952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'LASER, PLASMA ETCH, AND BACKSIDE GRIND PROCESS FOR WAFER DICING' [patent_app_type] => utility [patent_app_number] => 14/466671 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5728 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466671
LASER, PLASMA ETCH, AND BACKSIDE GRIND PROCESS FOR WAFER DICING Aug 21, 2014 Abandoned
Array ( [id] => 10418171 [patent_doc_number] => 20150303181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/466921 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6692 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466921
Semiconductor package and method for manufacturing the same Aug 21, 2014 Issued
Array ( [id] => 10370379 [patent_doc_number] => 20150255385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/465573 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8409 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465573 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465573
Semiconductor device and method of fabricating the same Aug 20, 2014 Issued
Array ( [id] => 10385305 [patent_doc_number] => 20150270312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/465047 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4481 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465047
Semiconductor device Aug 20, 2014 Issued
Array ( [id] => 10710049 [patent_doc_number] => 20160056196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'CONDUCTION LAYER FOR STACKED CIS CHARGING PREVENTION' [patent_app_type] => utility [patent_app_number] => 14/464035 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6083 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464035 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464035
Conduction layer for stacked CIS charging prevention Aug 19, 2014 Issued
Array ( [id] => 10440504 [patent_doc_number] => 20150325516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'CORELESS PACKAGING SUBSTRATE, POP STRUCTURE, AND METHODS FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/464051 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2918 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464051
CORELESS PACKAGING SUBSTRATE, POP STRUCTURE, AND METHODS FOR FABRICATING THE SAME Aug 19, 2014 Abandoned
Array ( [id] => 10710084 [patent_doc_number] => 20160056230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'GUARD RING STRUCTURE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/464298 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5854 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464298
Guard ring structure and method of forming the same Aug 19, 2014 Issued
Array ( [id] => 10681595 [patent_doc_number] => 20160027740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/463999 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2807 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463999 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463999
Package structure and method for fabricating the same Aug 19, 2014 Issued
Array ( [id] => 9864847 [patent_doc_number] => 20150044866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'INTERCONNECTION OF SEVERAL LEVELS OF A STACK OF SUPPORTS\nFOR ELECTRONIC COMPONENTS' [patent_app_type] => utility [patent_app_number] => 14/454023 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454023 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454023
Interconnection of several levels of a stack of supports for electronic components Aug 6, 2014 Issued
Array ( [id] => 11360387 [patent_doc_number] => 09537046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Optical device wafer processing method' [patent_app_type] => utility [patent_app_number] => 14/453131 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 8589 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/453131
Optical device wafer processing method Aug 5, 2014 Issued
Array ( [id] => 11214692 [patent_doc_number] => 09443732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/452243 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6788 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452243 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452243
Method of fabricating semiconductor device Aug 4, 2014 Issued
Array ( [id] => 11508697 [patent_doc_number] => 09599852 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Manufacturing of liquid crystal lenses using carrier substrate' [patent_app_type] => utility [patent_app_number] => 14/451732 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3288 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14451732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/451732
Manufacturing of liquid crystal lenses using carrier substrate Aug 4, 2014 Issued
Array ( [id] => 9864822 [patent_doc_number] => 20150044841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'METHOD FOR FORMING DOPED AREAS UNDER TRANSISTOR SPACERS' [patent_app_type] => utility [patent_app_number] => 14/450385 [patent_app_country] => US [patent_app_date] => 2014-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4223 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/450385
Method for forming doped areas under transistor spacers Aug 3, 2014 Issued
Array ( [id] => 11180771 [patent_doc_number] => 09412769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Transistor, method of manufacturing the transistor, and electronic device including the transistor' [patent_app_type] => utility [patent_app_number] => 14/450913 [patent_app_country] => US [patent_app_date] => 2014-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 7736 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450913 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/450913
Transistor, method of manufacturing the transistor, and electronic device including the transistor Aug 3, 2014 Issued
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