Search

Pamela E. Perkins

Examiner (ID: 8226, Phone: (571)272-1840 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
888
Issued Applications
738
Pending Applications
17
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9463440 [patent_doc_number] => 20140127867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL' [patent_app_type] => utility [patent_app_number] => 14/151200 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/151200
Silicon controlled rectifier structure with improved junction breakdown and leakage control Jan 8, 2014 Issued
Array ( [id] => 9421859 [patent_doc_number] => 20140106510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'DIE MOUNTING SUBSTRATE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/107836 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3600 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107836 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107836
DIE MOUNTING SUBSTRATE AND METHOD OF FABRICATING THE SAME Dec 15, 2013 Abandoned
Array ( [id] => 9537791 [patent_doc_number] => 20140162438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'Devices Formed from a Non-Polar Plane of a Crystalline Material and Method of Making the Same' [patent_app_type] => utility [patent_app_number] => 14/106454 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9405 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/106454
Devices formed from a non-polar plane of a crystalline material and method of making the same Dec 12, 2013 Issued
Array ( [id] => 9823964 [patent_doc_number] => 08933449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Apparatus having a dielectric containing scandium and gadolinium' [patent_app_type] => utility [patent_app_number] => 14/099107 [patent_app_country] => US [patent_app_date] => 2013-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9241 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099107 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/099107
Apparatus having a dielectric containing scandium and gadolinium Dec 5, 2013 Issued
Array ( [id] => 9944062 [patent_doc_number] => 08993363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Optoelectronic devices and applications thereof' [patent_app_type] => utility [patent_app_number] => 14/087458 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14352 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087458 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087458
Optoelectronic devices and applications thereof Nov 21, 2013 Issued
Array ( [id] => 9523974 [patent_doc_number] => 08748237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Memory device having an integrated two-terminal current limiting resistor' [patent_app_type] => utility [patent_app_number] => 14/064787 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 18289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064787
Memory device having an integrated two-terminal current limiting resistor Oct 27, 2013 Issued
Array ( [id] => 9905781 [patent_doc_number] => 20150060981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'STACKED NANOWIRE' [patent_app_type] => utility [patent_app_number] => 14/044131 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 2915 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044131
Stacked nanowire Oct 1, 2013 Issued
Array ( [id] => 9905877 [patent_doc_number] => 20150061077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION' [patent_app_type] => utility [patent_app_number] => 14/042889 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2548 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042889
Trench sidewall protection for selective epitaxial semiconductor material formation Sep 30, 2013 Issued
Array ( [id] => 9905818 [patent_doc_number] => 20150061018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME' [patent_app_type] => utility [patent_app_number] => 14/027331 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4347 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14027331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/027331
Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same Sep 15, 2013 Issued
Array ( [id] => 9212145 [patent_doc_number] => 20140011322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'Memory Cells and Methods of Making Memory Cells' [patent_app_type] => utility [patent_app_number] => 14/024836 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5842 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024836 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/024836
Methods of making memory cells Sep 11, 2013 Issued
Array ( [id] => 9905817 [patent_doc_number] => 20150061017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/024116 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4386 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/024116
Semiconductor devices and methods of manufacture Sep 10, 2013 Issued
Array ( [id] => 11787470 [patent_doc_number] => 09396929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Method of manufacturing a semiconductor device, substrate processing apparatus and recording medium' [patent_app_type] => utility [patent_app_number] => 14/021549 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 16948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021549 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/021549
Method of manufacturing a semiconductor device, substrate processing apparatus and recording medium Sep 8, 2013 Issued
Array ( [id] => 10932661 [patent_doc_number] => 20140335683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'METHOD FOR PRODUCING GALLIUM NITRIDE' [patent_app_type] => utility [patent_app_number] => 14/021108 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1668 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021108 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/021108
METHOD FOR PRODUCING GALLIUM NITRIDE Sep 8, 2013 Abandoned
Array ( [id] => 10888104 [patent_doc_number] => 08912100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-16 [patent_title] => 'Manufacturing method of complementary metal oxide semiconductor' [patent_app_type] => utility [patent_app_number] => 14/020470 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1800 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020470 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/020470
Manufacturing method of complementary metal oxide semiconductor Sep 5, 2013 Issued
Array ( [id] => 9909668 [patent_doc_number] => 20150064869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'Method of forming Fin-FET' [patent_app_type] => utility [patent_app_number] => 14/018439 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3205 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018439 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018439
Method of forming Fin-FET Sep 4, 2013 Issued
Array ( [id] => 9756861 [patent_doc_number] => 20140287563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/019223 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2079 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14019223 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/019223
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Sep 4, 2013 Abandoned
Array ( [id] => 9491164 [patent_doc_number] => 20140141569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING THROUGH-VIA AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/018630 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 8102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018630
SEMICONDUCTOR DEVICES HAVING THROUGH-VIA AND METHODS OF FABRICATING THE SAME Sep 4, 2013 Abandoned
Array ( [id] => 9909653 [patent_doc_number] => 20150064854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME' [patent_app_type] => utility [patent_app_number] => 14/017461 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3793 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017461
Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same Sep 3, 2013 Issued
14/003026 Manufacturing Method for LTPS TFT Sep 3, 2013
Array ( [id] => 10525494 [patent_doc_number] => 09252014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Trench sidewall protection for selective epitaxial semiconductor material formation' [patent_app_type] => utility [patent_app_number] => 14/017443 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2512 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017443 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017443
Trench sidewall protection for selective epitaxial semiconductor material formation Sep 3, 2013 Issued
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