
Pancham Bakshi
Examiner (ID: 11748, Phone: (571)270-3463 , Office: P/1671 )
| Most Active Art Unit | 1623 |
| Art Unit(s) | 1621, 1671, 1623, 1673 |
| Total Applications | 1483 |
| Issued Applications | 1026 |
| Pending Applications | 175 |
| Abandoned Applications | 342 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14446491
[patent_doc_number] => 20190181119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => STACKED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/834519
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834519
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834519 | STACKED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | Dec 6, 2017 | Abandoned |
Array
(
[id] => 13785823
[patent_doc_number] => 20190006450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR ELEMENT, ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING A SEMICONDUCTOR ELEMENT, AND METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/834628
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13176
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834628
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834628 | METHOD OF MANUFACTURING A SEMICONDUCTOR ELEMENT, ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING A SEMICONDUCTOR ELEMENT, AND METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY DEVICE | Dec 6, 2017 | Abandoned |
Array
(
[id] => 14446755
[patent_doc_number] => 20190181251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => MESH STRUCTURE FOR HETEROJUNCTION BIPOLAR TRANSISTORS FOR RF APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 15/834100
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834100
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834100 | MESH STRUCTURE FOR HETEROJUNCTION BIPOLAR TRANSISTORS FOR RF APPLICATIONS | Dec 6, 2017 | Abandoned |
Array
(
[id] => 14446701
[patent_doc_number] => 20190181224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => FORMATION OF SELF-LIMITED INNER SPACER FOR GATE-ALL-AROUND NANOSHEET FET
[patent_app_type] => utility
[patent_app_number] => 15/834380
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6475
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834380
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834380 | Formation of self-limited inner spacer for gate-all-around nanosheet FET | Dec 6, 2017 | Issued |
Array
(
[id] => 14446683
[patent_doc_number] => 20190181215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => ON-CHIP RESISTORS WITH DIRECT WIRING CONNECTIONS
[patent_app_type] => utility
[patent_app_number] => 15/834443
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4368
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834443
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834443 | On-chip resistors with direct wiring connections | Dec 6, 2017 | Issued |
Array
(
[id] => 12823756
[patent_doc_number] => 20180166424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-14
[patent_title] => LIGHT-EMITTING DIODE (LED) DEVICE FOR REALIZING MULTI-COLORS
[patent_app_type] => utility
[patent_app_number] => 15/833495
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10168
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833495
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833495 | Light-emitting diode (LED) device for realizing multi-colors | Dec 5, 2017 | Issued |
Array
(
[id] => 15015369
[patent_doc_number] => 10453844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-22
[patent_title] => Techniques for enhancing vertical gate-all-around FET performance
[patent_app_type] => utility
[patent_app_number] => 15/833543
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 6800
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833543
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833543 | Techniques for enhancing vertical gate-all-around FET performance | Dec 5, 2017 | Issued |
Array
(
[id] => 14801435
[patent_doc_number] => 10403729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-03
[patent_title] => Semiconductor devices and contact plugs
[patent_app_type] => utility
[patent_app_number] => 15/833148
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 33
[patent_no_of_words] => 12271
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833148
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833148 | Semiconductor devices and contact plugs | Dec 5, 2017 | Issued |
Array
(
[id] => 13452117
[patent_doc_number] => 20180277601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MATERIAL LAYER
[patent_app_type] => utility
[patent_app_number] => 15/832958
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832958
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/832958 | Memory device including a variable resistance material layer | Dec 5, 2017 | Issued |
Array
(
[id] => 12872803
[patent_doc_number] => 20180182776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => VERTICAL MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/833342
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9368
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833342
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833342 | Vertical memory devices | Dec 5, 2017 | Issued |
Array
(
[id] => 12849910
[patent_doc_number] => 20180175143
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/833031
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6935
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833031
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833031 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Dec 5, 2017 | Abandoned |
Array
(
[id] => 14011907
[patent_doc_number] => 10224430
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-03-05
[patent_title] => Thin film transistors with epitaxial source/drain and drain field relief
[patent_app_type] => utility
[patent_app_number] => 15/833120
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 45
[patent_no_of_words] => 9860
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833120
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833120 | Thin film transistors with epitaxial source/drain and drain field relief | Dec 5, 2017 | Issued |
Array
(
[id] => 15823051
[patent_doc_number] => 10636721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Semiconductor package and electronic device having the same
[patent_app_type] => utility
[patent_app_number] => 15/832807
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6603
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832807
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/832807 | Semiconductor package and electronic device having the same | Dec 5, 2017 | Issued |
Array
(
[id] => 12615078
[patent_doc_number] => 20180096856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => SUBSTRATE TREATING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 15/833184
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6426
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833184
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833184 | Substrate treating apparatus | Dec 5, 2017 | Issued |
Array
(
[id] => 15376219
[patent_doc_number] => 10529838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-07
[patent_title] => Semiconductor device having a variable carbon concentration
[patent_app_type] => utility
[patent_app_number] => 15/831247
[patent_app_country] => US
[patent_app_date] => 2017-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7506
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831247
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/831247 | Semiconductor device having a variable carbon concentration | Dec 3, 2017 | Issued |
Array
(
[id] => 12554574
[patent_doc_number] => 10014417
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-03
[patent_title] => Solid state imaging apparatus, production method thereof and electronic device
[patent_app_type] => utility
[patent_app_number] => 15/830935
[patent_app_country] => US
[patent_app_date] => 2017-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 50
[patent_no_of_words] => 13643
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830935
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/830935 | Solid state imaging apparatus, production method thereof and electronic device | Dec 3, 2017 | Issued |
Array
(
[id] => 12263796
[patent_doc_number] => 20180082991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/824422
[patent_app_country] => US
[patent_app_date] => 2017-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17488
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824422
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/824422 | Semiconductor device | Nov 27, 2017 | Issued |
Array
(
[id] => 13485577
[patent_doc_number] => 20180294331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-11
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/823961
[patent_app_country] => US
[patent_app_date] => 2017-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10975
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823961
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/823961 | Semiconductor device | Nov 27, 2017 | Issued |
Array
(
[id] => 12595632
[patent_doc_number] => 20180090374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
[patent_app_type] => utility
[patent_app_number] => 15/817554
[patent_app_country] => US
[patent_app_date] => 2017-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817554
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/817554 | Two-dimensional self-aligned super via integration on self-aligned gate contact | Nov 19, 2017 | Issued |
Array
(
[id] => 15791725
[patent_doc_number] => 10629594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-21
[patent_title] => Diode including a Zener diode region
[patent_app_type] => utility
[patent_app_number] => 15/816387
[patent_app_country] => US
[patent_app_date] => 2017-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 25
[patent_no_of_words] => 8831
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816387
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/816387 | Diode including a Zener diode region | Nov 16, 2017 | Issued |