Search

Pancham Bakshi

Examiner (ID: 11748, Phone: (571)270-3463 , Office: P/1671 )

Most Active Art Unit
1623
Art Unit(s)
1621, 1671, 1623, 1673
Total Applications
1483
Issued Applications
1026
Pending Applications
175
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14205243 [patent_doc_number] => 10269744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor device with thin redistribution layers [patent_app_type] => utility [patent_app_number] => 15/812741 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812741
Semiconductor device with thin redistribution layers Nov 13, 2017 Issued
Array ( [id] => 15656971 [patent_doc_number] => 20200091016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => MANUFACTURING METHOD AND INSPECTION METHOD OF GROUP-III NITRIDE LAMINATE, AND GROUP-III NITRIDE LAMINATE [patent_app_type] => utility [patent_app_number] => 16/472968 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16472968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/472968
MANUFACTURING METHOD AND INSPECTION METHOD OF GROUP-III NITRIDE LAMINATE, AND GROUP-III NITRIDE LAMINATE Nov 8, 2017 Abandoned
Array ( [id] => 13528427 [patent_doc_number] => 20180315756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => VERTICAL TRANSPORT TRANSISTORS WITH EQUAL GATE STACK THICKNESSES [patent_app_type] => utility [patent_app_number] => 15/806759 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806759 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806759
Vertical transport transistors with equal gate stack thicknesses Nov 7, 2017 Issued
Array ( [id] => 12236119 [patent_doc_number] => 20180068982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/800127 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800127
Chip assembly Oct 31, 2017 Issued
Array ( [id] => 12236073 [patent_doc_number] => 20180068936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/796746 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7065 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796746 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796746
Semiconductor device and method of manufacturing the same Oct 26, 2017 Issued
Array ( [id] => 12188733 [patent_doc_number] => 20180047669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'III-V COMPATIBLE ANTI-FUSES' [patent_app_type] => utility [patent_app_number] => 15/792356 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8622 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792356
III-V compatible anti-fuses Oct 23, 2017 Issued
Array ( [id] => 12141268 [patent_doc_number] => 20180019351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'NITRIDE UV LIGHT SENSORS ON SILICON SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 15/718612 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2486 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718612
Nitride UV light sensors on silicon substrates Sep 27, 2017 Issued
Array ( [id] => 12141153 [patent_doc_number] => 20180019236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'Method and Structure of Three-Dimensional Chip Stacking' [patent_app_type] => utility [patent_app_number] => 15/714191 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 5669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714191
Method and structure of three-dimensional chip stacking Sep 24, 2017 Issued
Array ( [id] => 14630635 [patent_doc_number] => 20190228686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => DISPLAY APPARATUS AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/333607 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16333607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/333607
Display apparatus and method for manufacturing same Sep 20, 2017 Issued
Array ( [id] => 13159673 [patent_doc_number] => 10096571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Chip-on-wafer package and method of forming same [patent_app_type] => utility [patent_app_number] => 15/703716 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 11332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703716 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703716
Chip-on-wafer package and method of forming same Sep 12, 2017 Issued
Array ( [id] => 13724635 [patent_doc_number] => 20170373273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/699113 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699113
Display Device Sep 7, 2017 Issued
Array ( [id] => 13293363 [patent_doc_number] => 10157882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => 3D chip-on-wafer-on-substrate structure with via last process [patent_app_type] => utility [patent_app_number] => 15/695553 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 7680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695553
3D chip-on-wafer-on-substrate structure with via last process Sep 4, 2017 Issued
Array ( [id] => 13996041 [patent_doc_number] => 20190067178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => FINE PITCH AND SPACING INTERCONNECTS WITH RESERVE INTERCONNECT PORTION [patent_app_type] => utility [patent_app_number] => 15/690541 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690541
FINE PITCH AND SPACING INTERCONNECTS WITH RESERVE INTERCONNECT PORTION Aug 29, 2017 Abandoned
Array ( [id] => 15166445 [patent_doc_number] => 10488710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Array substrate and method for manufacturing the same, and display apparatus [patent_app_type] => utility [patent_app_number] => 15/691203 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2863 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691203 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691203
Array substrate and method for manufacturing the same, and display apparatus Aug 29, 2017 Issued
Array ( [id] => 17018375 [patent_doc_number] => 11088020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Structure and formation method of interconnection structure of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/691035 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 11144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691035
Structure and formation method of interconnection structure of semiconductor device Aug 29, 2017 Issued
Array ( [id] => 13996097 [patent_doc_number] => 20190067206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/691055 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691055
Apparatuses and methods for shielded memory architecture Aug 29, 2017 Issued
Array ( [id] => 16280297 [patent_doc_number] => 10763338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Silicide implants [patent_app_type] => utility [patent_app_number] => 15/690693 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690693 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690693
Silicide implants Aug 29, 2017 Issued
Array ( [id] => 13451889 [patent_doc_number] => 20180277487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => GRAPHENE WIRING STRUCTURE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING GRAPHENE WIRING STRUCTURE, AND METHOD FOR MANUFACTURING WIRING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/691257 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691257
Graphene wiring structure and semiconductor device using the same Aug 29, 2017 Issued
Array ( [id] => 13349715 [patent_doc_number] => 20180226397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRICAL APPARATUS [patent_app_type] => utility [patent_app_number] => 15/690606 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690606
Semiconductor device and electrical apparatus Aug 29, 2017 Issued
Array ( [id] => 16820092 [patent_doc_number] => 11004931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/690641 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 8634 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690641 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690641
Semiconductor device Aug 29, 2017 Issued
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