Search

Paras D. Shah

Examiner (ID: 9016, Phone: (571)270-1650 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2653, 2626, 2659
Total Applications
738
Issued Applications
515
Pending Applications
27
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18456272 [patent_doc_number] => 20230197554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => THERMAL BRIDGE INTERPOSER STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/558508 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558508
Thermal bridge interposer structure Dec 20, 2021 Issued
Array ( [id] => 18456424 [patent_doc_number] => 20230197706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTEGRATED DECOUPLING AND ALIGNMENT FEATURES [patent_app_type] => utility [patent_app_number] => 17/555712 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555712
Method for fabricating semiconductor device with integrated decoupling and alignment features Dec 19, 2021 Issued
Array ( [id] => 17660835 [patent_doc_number] => 20220181300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MULTI-TIER BACKSIDE POWER DELIVERY NETWORK FOR DENSE GATE-ON-GATE 3D LOGIC [patent_app_type] => utility [patent_app_number] => 17/541581 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541581 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541581
Multi-tier backside power delivery network for dense gate-on-gate 3D logic Dec 2, 2021 Issued
Array ( [id] => 17933329 [patent_doc_number] => 20220328455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => VERTICAL INTERCONNECT STRUCTURES IN THREE-DIMENSIONAL INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/538029 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538029
Vertical interconnect structures in three-dimensional integrated circuits Nov 29, 2021 Issued
Array ( [id] => 17886610 [patent_doc_number] => 20220302088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => VERTICAL INTERCONNECT STRUCTURES WITH INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/537026 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537026
Vertical interconnect structures with integrated circuits Nov 28, 2021 Issued
Array ( [id] => 17477484 [patent_doc_number] => 20220084988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/536019 [patent_app_country] => US [patent_app_date] => 2021-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536019
3D semiconductor device and structure with metal layers Nov 26, 2021 Issued
Array ( [id] => 19138082 [patent_doc_number] => 11973058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Multiple die assembly [patent_app_type] => utility [patent_app_number] => 17/535664 [patent_app_country] => US [patent_app_date] => 2021-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535664
Multiple die assembly Nov 24, 2021 Issued
Array ( [id] => 18394891 [patent_doc_number] => 20230163112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/456068 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456068 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456068
Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods Nov 21, 2021 Issued
Array ( [id] => 18913100 [patent_doc_number] => 11876088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Shared well structure, layout, and method [patent_app_type] => utility [patent_app_number] => 17/527883 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 16189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527883
Shared well structure, layout, and method Nov 15, 2021 Issued
Array ( [id] => 18415974 [patent_doc_number] => 11670520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Package structure with interconnection between chips and packaging method thereof [patent_app_type] => utility [patent_app_number] => 17/523093 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 7144 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523093
Package structure with interconnection between chips and packaging method thereof Nov 9, 2021 Issued
Array ( [id] => 19271723 [patent_doc_number] => 20240215430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => STRETCHABLE DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/799807 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/799807
Stretchable display substrate and manufacturing method thereof Nov 9, 2021 Issued
Array ( [id] => 18362615 [patent_doc_number] => 20230144206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => PACKAGING ARCHITECTURES FOR SUB-TERAHERTZ RADIO FREQUENCY DEVICES [patent_app_type] => utility [patent_app_number] => 17/523655 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523655
Packaging architectures for sub-terahertz radio frequency devices Nov 9, 2021 Issued
Array ( [id] => 19376652 [patent_doc_number] => 12068232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Integrated circuit package with serpentine conductor and method of making [patent_app_type] => utility [patent_app_number] => 17/514722 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/514722
Integrated circuit package with serpentine conductor and method of making Oct 28, 2021 Issued
Array ( [id] => 18848821 [patent_doc_number] => 20230411225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => EVALUATION METHOD FOR SILICON CARBIDE SUBSTRATES [patent_app_type] => utility [patent_app_number] => 18/251124 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18251124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/251124
EVALUATION METHOD FOR SILICON CARBIDE SUBSTRATES Oct 26, 2021 Pending
Array ( [id] => 18321814 [patent_doc_number] => 20230119942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => Package with Compartmentalized Lid for Heat Spreader and EMI Shield [patent_app_type] => utility [patent_app_number] => 17/451036 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451036
Package with compartmentalized lid for heat spreader and EMI shield Oct 14, 2021 Issued
Array ( [id] => 18311440 [patent_doc_number] => 20230115340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => LEADLESS POWER AMPLIFIER PACKAGES INCLUDING TOPSIDE TERMINATION INTERPOSER ARRANGEMENTS AND METHODS FOR THE FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/491309 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491309
Leadless power amplifier packages including topside termination interposer arrangements and methods for the fabrication thereof Sep 29, 2021 Issued
Array ( [id] => 17360006 [patent_doc_number] => 20220020802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => IMAGE SENSOR AND METHOD FOR MANUFACTURING IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/488817 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488817
Image sensor and method for manufacturing image sensor Sep 28, 2021 Issued
Array ( [id] => 18304446 [patent_doc_number] => 11626360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Semiconductor device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/486829 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486829
Semiconductor device package and method for manufacturing the same Sep 26, 2021 Issued
Array ( [id] => 18371930 [patent_doc_number] => 11652112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => SLT integrated circuit capacitor structure and methods [patent_app_type] => utility [patent_app_number] => 17/486571 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7327 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486571
SLT integrated circuit capacitor structure and methods Sep 26, 2021 Issued
Array ( [id] => 17692194 [patent_doc_number] => 20220199487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 17/478991 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478991
Semiconductor device and semiconductor device fabrication method Sep 19, 2021 Issued
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