Search

Paras D. Shah

Examiner (ID: 9016, Phone: (571)270-1650 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2653, 2626, 2659
Total Applications
738
Issued Applications
515
Pending Applications
27
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17574134 [patent_doc_number] => 11322408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer [patent_app_type] => utility [patent_app_number] => 17/130214 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130214
Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer Dec 21, 2020 Issued
Array ( [id] => 16764512 [patent_doc_number] => 20210110094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING CELL REGION HAVING MORE SIMILAR CELL DENSITIES IN DIFFERENT HEIGHT ROWS, AND METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM OF SAME [patent_app_type] => utility [patent_app_number] => 17/131128 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131128
Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same Dec 21, 2020 Issued
Array ( [id] => 17692302 [patent_doc_number] => 20220199595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => INTEGRATED CIRCUIT PACKAGE HAVING A REDISTRIBUTION LAYER ABOVE A POWER MANAGEMENT INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/127722 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127722
INTEGRATED CIRCUIT PACKAGE HAVING A REDISTRIBUTION LAYER ABOVE A POWER MANAGEMENT INTEGRATED CIRCUIT Dec 17, 2020 Abandoned
Array ( [id] => 16752544 [patent_doc_number] => 20210104556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/123321 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123321
Semiconductor device and method for manufacturing the same Dec 15, 2020 Issued
Array ( [id] => 16951808 [patent_doc_number] => 20210210500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => SEMICONDUCTOR ASSEMBLIES INCLUDING COMBINATION MEMORY AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/124072 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124072
Semiconductor assemblies including combination memory and methods of manufacturing the same Dec 15, 2020 Issued
Array ( [id] => 17486014 [patent_doc_number] => 20220093518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/108399 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108399
Electronic package and manufacturing method thereof Nov 30, 2020 Issued
Array ( [id] => 17638139 [patent_doc_number] => 11348873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Wafer stacking method and wafer stacking structure [patent_app_type] => utility [patent_app_number] => 17/102182 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5187 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102182
Wafer stacking method and wafer stacking structure Nov 22, 2020 Issued
Array ( [id] => 17615521 [patent_doc_number] => 20220157801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => POWER MODULE PACKAGE FOR DIRECT COOLING MULTIPLE POWER MODULES [patent_app_type] => utility [patent_app_number] => 16/949896 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949896
Power module package for direct cooling multiple power modules Nov 18, 2020 Issued
Array ( [id] => 16873485 [patent_doc_number] => 20210166952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => MANUFACTURING A MODULE WITH SOLDER BODY HAVING ELEVATED EDGE [patent_app_type] => utility [patent_app_number] => 16/951633 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951633
Manufacturing a module with solder body having elevated edge Nov 17, 2020 Issued
Array ( [id] => 17615447 [patent_doc_number] => 20220157727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => Structure and Method for Bridge Chip Assembly with Capillary Underfill [patent_app_type] => utility [patent_app_number] => 16/950332 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950332
Structure and method for bridge chip assembly with capillary underfill Nov 16, 2020 Issued
Array ( [id] => 18190649 [patent_doc_number] => 11581251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Package comprising inter-substrate gradient interconnect structure [patent_app_type] => utility [patent_app_number] => 17/093954 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8862 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093954
Package comprising inter-substrate gradient interconnect structure Nov 9, 2020 Issued
Array ( [id] => 17908626 [patent_doc_number] => 11462488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Substrate cores for warpage control [patent_app_type] => utility [patent_app_number] => 17/090926 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6696 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090926
Substrate cores for warpage control Nov 5, 2020 Issued
Array ( [id] => 17623154 [patent_doc_number] => 11342218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Single crystalline silicon stack formation and bonding to a CMOS wafer [patent_app_type] => utility [patent_app_number] => 17/086536 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11446 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086536
Single crystalline silicon stack formation and bonding to a CMOS wafer Nov 1, 2020 Issued
Array ( [id] => 17395866 [patent_doc_number] => 11244890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Ground via clustering for crosstalk mitigation [patent_app_type] => utility [patent_app_number] => 17/074820 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074820
Ground via clustering for crosstalk mitigation Oct 19, 2020 Issued
Array ( [id] => 17262735 [patent_doc_number] => 20210375720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/075503 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075503
Memory device and method of manufacturing the same Oct 19, 2020 Issued
Array ( [id] => 19553890 [patent_doc_number] => 12137613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Polycyclic compound and organoelectro luminescent device using same [patent_app_type] => utility [patent_app_number] => 17/767819 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17767819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/767819
Polycyclic compound and organoelectro luminescent device using same Oct 11, 2020 Issued
Array ( [id] => 16625099 [patent_doc_number] => 20210043752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/068769 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068769
Semiconductor device Oct 11, 2020 Issued
Array ( [id] => 17818545 [patent_doc_number] => 11424167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/067565 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067565
Semiconductor package structure and method for manufacturing the same Oct 8, 2020 Issued
Array ( [id] => 17574094 [patent_doc_number] => 11322368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Method for fabricating semiconductor package [patent_app_type] => utility [patent_app_number] => 17/037003 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037003
Method for fabricating semiconductor package Sep 28, 2020 Issued
Array ( [id] => 17529900 [patent_doc_number] => 11302598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/034589 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034589
Semiconductor package Sep 27, 2020 Issued
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