Search

Paras D. Shah

Examiner (ID: 9016, Phone: (571)270-1650 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2653, 2626, 2659
Total Applications
738
Issued Applications
515
Pending Applications
27
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13667451 [patent_doc_number] => 10163905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Method and structure for FinFET device [patent_app_type] => utility [patent_app_number] => 15/700377 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 6595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700377
Method and structure for FinFET device Sep 10, 2017 Issued
Array ( [id] => 13293471 [patent_doc_number] => 10157936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/695162 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 48 [patent_no_of_words] => 26891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695162 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695162
Semiconductor device and method for manufacturing the same Sep 4, 2017 Issued
Array ( [id] => 13271317 [patent_doc_number] => 10147745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Array substrate, display panel and display device [patent_app_type] => utility [patent_app_number] => 15/693017 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6025 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693017
Array substrate, display panel and display device Aug 30, 2017 Issued
Array ( [id] => 13159739 [patent_doc_number] => 10096605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Semiconductor devices including a dummy gate structure on a fin [patent_app_type] => utility [patent_app_number] => 15/680960 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 89 [patent_figures_cnt] => 92 [patent_no_of_words] => 18766 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680960 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680960
Semiconductor devices including a dummy gate structure on a fin Aug 17, 2017 Issued
Array ( [id] => 13667673 [patent_doc_number] => 10164018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Semiconductor interconnect structure having graphene-capped metal interconnects [patent_app_type] => utility [patent_app_number] => 15/675535 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 11151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675535
Semiconductor interconnect structure having graphene-capped metal interconnects Aug 10, 2017 Issued
Array ( [id] => 12223367 [patent_doc_number] => 20180061727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/675612 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675612
Semiconductor device package and a method of manufacturing the same Aug 10, 2017 Issued
Array ( [id] => 12823483 [patent_doc_number] => 20180166333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE BARRIER LAYER [patent_app_type] => utility [patent_app_number] => 15/675498 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675498
Semiconductor interconnect structure having a graphene barrier layer Aug 10, 2017 Issued
Array ( [id] => 15015211 [patent_doc_number] => 10453764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Molding for large panel fan-out package [patent_app_type] => utility [patent_app_number] => 15/675610 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 85 [patent_no_of_words] => 8954 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675610 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675610
Molding for large panel fan-out package Aug 10, 2017 Issued
Array ( [id] => 12990283 [patent_doc_number] => 20170345837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/674135 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674135
Semiconductor memory device Aug 9, 2017 Issued
Array ( [id] => 12061982 [patent_doc_number] => 20170338326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'Two-Step Dummy Gate Formation' [patent_app_type] => utility [patent_app_number] => 15/669297 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669297 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669297
Two-step dummy gate formation Aug 3, 2017 Issued
Array ( [id] => 13159613 [patent_doc_number] => 10096541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Method for fabricating electronic package [patent_app_type] => utility [patent_app_number] => 15/666005 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3869 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/666005
Method for fabricating electronic package Jul 31, 2017 Issued
Array ( [id] => 13225689 [patent_doc_number] => 10126616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 15/662899 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 12975 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662899
Electronic device Jul 27, 2017 Issued
Array ( [id] => 13257559 [patent_doc_number] => 10141477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Strained AlGaInP layers for efficient electron and hole blocking in light emitting devices [patent_app_type] => utility [patent_app_number] => 15/662952 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662952
Strained AlGaInP layers for efficient electron and hole blocking in light emitting devices Jul 27, 2017 Issued
Array ( [id] => 12027172 [patent_doc_number] => 20170317271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'METHOD FOR DOPING AN ACTIVE HALL EFFECT REGION OF A HALL EFFECT DEVICE AND HALL EFFECT DEVICE HAVING A DOPED ACTIVE HALL EFFECT REGION' [patent_app_type] => utility [patent_app_number] => 15/652579 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652579
Method for doping an active hall effect region of a hall effect device Jul 17, 2017 Issued
Array ( [id] => 12452514 [patent_doc_number] => 09983363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Optical semiconductor device [patent_app_type] => utility [patent_app_number] => 15/650857 [patent_app_country] => US [patent_app_date] => 2017-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5253 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650857 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650857
Optical semiconductor device Jul 14, 2017 Issued
Array ( [id] => 14087713 [patent_doc_number] => 10239746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Vertical stopper for capping MEMS devices [patent_app_type] => utility [patent_app_number] => 15/650822 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5790 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650822
Vertical stopper for capping MEMS devices Jul 13, 2017 Issued
Array ( [id] => 14475829 [patent_doc_number] => 20190189562 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-06-20 [patent_title] => SYSTEM ON INTEGRATED CHIPS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/650495 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650495
System on integrated chips and methods of forming the same Jul 13, 2017 Issued
Array ( [id] => 14475829 [patent_doc_number] => 20190189562 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-06-20 [patent_title] => SYSTEM ON INTEGRATED CHIPS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/650495 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650495
System on integrated chips and methods of forming the same Jul 13, 2017 Issued
Array ( [id] => 14366817 [patent_doc_number] => 10304720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Laser ablative dielectric material [patent_app_type] => utility [patent_app_number] => 15/650535 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650535
Laser ablative dielectric material Jul 13, 2017 Issued
Array ( [id] => 13832861 [patent_doc_number] => 20190019915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => METHOD OF MANUFACTURING A 3 COLOR LED INTEGRATED SI CMOS DRIVER WAFER USING DIE TO WAFER BONDING APPROACH [patent_app_type] => utility [patent_app_number] => 15/650427 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650427
Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach Jul 13, 2017 Issued
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