Search

Parthkumar Patel

Examiner (ID: 9642, Phone: (571)270-1970 , Office: P/2468 )

Most Active Art Unit
2468
Art Unit(s)
2479, 2468
Total Applications
911
Issued Applications
683
Pending Applications
91
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15461795 [patent_doc_number] => 20200043722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => CVD BASED SPACER DEPOSITION WITH ZERO LOADING [patent_app_type] => utility [patent_app_number] => 16/514534 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514534
CVD BASED SPACER DEPOSITION WITH ZERO LOADING Jul 16, 2019 Abandoned
Array ( [id] => 16586046 [patent_doc_number] => 20210020448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Method and Structure for Smoothing Substrate Patterns or Surfaces [patent_app_type] => utility [patent_app_number] => 16/513602 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513602 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513602
Method and Structure for Smoothing Substrate Patterns or Surfaces Jul 15, 2019 Abandoned
Array ( [id] => 15597587 [patent_doc_number] => 20200075328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => EPITAXY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/513657 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513657
Epitaxy substrate and method of manufacturing the same Jul 15, 2019 Issued
Array ( [id] => 17730729 [patent_doc_number] => 11387130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Substrate alignment systems and related methods [patent_app_type] => utility [patent_app_number] => 16/505949 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3301 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505949
Substrate alignment systems and related methods Jul 8, 2019 Issued
Array ( [id] => 17002654 [patent_doc_number] => 11081477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-03 [patent_title] => IC with test structures and e-beam pads embedded within a contiguous standard cell area [patent_app_type] => utility [patent_app_number] => 16/458087 [patent_app_country] => US [patent_app_date] => 2019-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 146 [patent_figures_cnt] => 251 [patent_no_of_words] => 25311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 485 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458087
IC with test structures and e-beam pads embedded within a contiguous standard cell area Jun 29, 2019 Issued
Array ( [id] => 17002653 [patent_doc_number] => 11081476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-03 [patent_title] => IC with test structures and e-beam pads embedded within a contiguous standard cell area [patent_app_type] => utility [patent_app_number] => 16/458085 [patent_app_country] => US [patent_app_date] => 2019-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 146 [patent_figures_cnt] => 251 [patent_no_of_words] => 25313 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 484 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458085
IC with test structures and e-beam pads embedded within a contiguous standard cell area Jun 29, 2019 Issued
Array ( [id] => 17063194 [patent_doc_number] => 11107804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => IC with test structures and e-beam pads embedded within a contiguous standard cell area [patent_app_type] => utility [patent_app_number] => 16/458095 [patent_app_country] => US [patent_app_date] => 2019-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 146 [patent_figures_cnt] => 252 [patent_no_of_words] => 25316 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 486 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458095 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458095
IC with test structures and e-beam pads embedded within a contiguous standard cell area Jun 29, 2019 Issued
Array ( [id] => 16846030 [patent_doc_number] => 11018126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => IC with test structures and e-beam pads embedded within a contiguous standard cell area [patent_app_type] => utility [patent_app_number] => 16/458082 [patent_app_country] => US [patent_app_date] => 2019-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 146 [patent_figures_cnt] => 248 [patent_no_of_words] => 25303 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 485 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458082
IC with test structures and e-beam pads embedded within a contiguous standard cell area Jun 29, 2019 Issued
Array ( [id] => 16988011 [patent_doc_number] => 11075194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => IC with test structures and E-beam pads embedded within a contiguous standard cell area [patent_app_type] => utility [patent_app_number] => 16/458088 [patent_app_country] => US [patent_app_date] => 2019-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 146 [patent_figures_cnt] => 251 [patent_no_of_words] => 25313 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 487 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458088
IC with test structures and E-beam pads embedded within a contiguous standard cell area Jun 29, 2019 Issued
Array ( [id] => 16759881 [patent_doc_number] => 10978438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => IC with test structures and E-beam pads embedded within a contiguous standard cell area [patent_app_type] => utility [patent_app_number] => 16/458042 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 146 [patent_figures_cnt] => 251 [patent_no_of_words] => 25199 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458042
IC with test structures and E-beam pads embedded within a contiguous standard cell area Jun 28, 2019 Issued
Array ( [id] => 16545302 [patent_doc_number] => 20200411717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MICRO LIGHT-EMITTING DIODE DISPLAYS HAVING COLOR CORRECTION FILMS APPLIED THERETO [patent_app_type] => utility [patent_app_number] => 16/455673 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455673
Micro light-emitting diode displays having color correction films applied thereto Jun 26, 2019 Issued
Array ( [id] => 17559106 [patent_doc_number] => 11315828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Metal oxide composite as etch stop layer [patent_app_type] => utility [patent_app_number] => 16/451432 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451432
Metal oxide composite as etch stop layer Jun 24, 2019 Issued
Array ( [id] => 15294395 [patent_doc_number] => 20190390333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANAGING PARTS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 16/451507 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451507
Method of manufacturing semiconductor device, method of managing parts, and recording medium Jun 24, 2019 Issued
Array ( [id] => 16264715 [patent_doc_number] => 10756163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Conformal capacitor structure formed by a single process [patent_app_type] => utility [patent_app_number] => 16/448921 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6941 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448921
Conformal capacitor structure formed by a single process Jun 20, 2019 Issued
Array ( [id] => 16528639 [patent_doc_number] => 20200402720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => EMBEDDED THIN FILM CAPACITOR WITH NANOCUBE FILM AND PROCESS FOR FORMING SUCH [patent_app_type] => utility [patent_app_number] => 16/447877 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447877 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447877
EMBEDDED THIN FILM CAPACITOR WITH NANOCUBE FILM AND PROCESS FOR FORMING SUCH Jun 19, 2019 Abandoned
Array ( [id] => 17002672 [patent_doc_number] => 11081495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Integrated structures [patent_app_type] => utility [patent_app_number] => 16/438334 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/438334
Integrated structures Jun 10, 2019 Issued
Array ( [id] => 15260437 [patent_doc_number] => 20190378952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => ENABLING LOW-COST III-V/SI INTEGRATION THROUGH NUCLEATION OF GAP ON V-GROOVED SI SUBSTRATES [patent_app_type] => utility [patent_app_number] => 16/436373 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/436373
ENABLING LOW-COST III-V/SI INTEGRATION THROUGH NUCLEATION OF GAP ON V-GROOVED SI SUBSTRATES Jun 9, 2019 Abandoned
Array ( [id] => 16509393 [patent_doc_number] => 20200388649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => MULTI-LEVEL LOOP CUT PROCESS FOR A THREE-DIMENSIONAL MEMORY DEVICE USING PITCH-DOUBLED METAL LINES [patent_app_type] => utility [patent_app_number] => 16/436185 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/436185
Multi-level loop cut process for a three-dimensional memory device using pitch-doubled metal lines Jun 9, 2019 Issued
Array ( [id] => 16574928 [patent_doc_number] => 10896855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Asymmetric gate spacer formation using multiple ion implants [patent_app_type] => utility [patent_app_number] => 16/436296 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3366 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/436296
Asymmetric gate spacer formation using multiple ion implants Jun 9, 2019 Issued
Array ( [id] => 16509262 [patent_doc_number] => 20200388518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => WAFER PLACEMENT ERROR DETECTION BASED ON MEASURING A CURRENT THROUGH AN ELECTROSTATIC CHUCK AND SOLUTION FOR INTERVENTION [patent_app_type] => utility [patent_app_number] => 16/431564 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431564
Wafer placement error detection based on measuring a current through an electrostatic chuck and solution for intervention Jun 3, 2019 Issued
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