Search

Parthkumar Patel

Examiner (ID: 9642, Phone: (571)270-1970 , Office: P/2468 )

Most Active Art Unit
2468
Art Unit(s)
2479, 2468
Total Applications
911
Issued Applications
683
Pending Applications
91
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16509252 [patent_doc_number] => 20200388508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE [patent_app_type] => utility [patent_app_number] => 16/431613 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431613
REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE Jun 3, 2019 Pending
Array ( [id] => 16509232 [patent_doc_number] => 20200388488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => BOTTOM-UP CURING OF DIELECTRIC FILMS IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/431121 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431121
BOTTOM-UP CURING OF DIELECTRIC FILMS IN INTEGRATED CIRCUITS Jun 3, 2019 Abandoned
Array ( [id] => 16509275 [patent_doc_number] => 20200388531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => ION IMPLANTATION ASSISTED CURING FOR FLOWABLE POROUS DIELECTRICS [patent_app_type] => utility [patent_app_number] => 16/431186 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431186 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431186
ION IMPLANTATION ASSISTED CURING FOR FLOWABLE POROUS DIELECTRICS Jun 3, 2019 Abandoned
Array ( [id] => 14875425 [patent_doc_number] => 20190287954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SOLID STATE TRANSDUCERS WITH STATE DETECTION, AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/422413 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422413
Solid state transducers with state detection, and associated systems and methods May 23, 2019 Issued
Array ( [id] => 14904927 [patent_doc_number] => 20190296229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MAGNETORESISTIVE ELEMENT AND MAGNETIC SENSOR [patent_app_type] => utility [patent_app_number] => 16/414823 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414823 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414823
Magnetoresistive element and magnetic sensor May 16, 2019 Issued
Array ( [id] => 14785001 [patent_doc_number] => 20190267398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/411307 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411307
Non-volatile memory device May 13, 2019 Issued
Array ( [id] => 17137712 [patent_doc_number] => 11139279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Light-emitting diode device [patent_app_type] => utility [patent_app_number] => 16/389263 [patent_app_country] => US [patent_app_date] => 2019-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16389263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/389263
Light-emitting diode device Apr 18, 2019 Issued
Array ( [id] => 16553217 [patent_doc_number] => 10886385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Semiconductor structures having increased channel strain using fin release in gate regions [patent_app_type] => utility [patent_app_number] => 16/375890 [patent_app_country] => US [patent_app_date] => 2019-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/375890
Semiconductor structures having increased channel strain using fin release in gate regions Apr 4, 2019 Issued
Array ( [id] => 14631423 [patent_doc_number] => 20190229081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/372437 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372437 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372437
Semiconductor devices Apr 1, 2019 Issued
Array ( [id] => 16348014 [patent_doc_number] => 20200312665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => HYBRID FINE LINE SPACING ARCHITECTURE FOR BUMP PITCH SCALING [patent_app_type] => utility [patent_app_number] => 16/363688 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363688
Hybrid fine line spacing architecture for bump pitch scaling Mar 24, 2019 Issued
Array ( [id] => 17033062 [patent_doc_number] => 11094882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Method of manufacturing memory device [patent_app_type] => utility [patent_app_number] => 16/360500 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 4640 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360500
Method of manufacturing memory device Mar 20, 2019 Issued
Array ( [id] => 17825723 [patent_doc_number] => 11430677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Wafer taping apparatus and method [patent_app_type] => utility [patent_app_number] => 16/360505 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360505 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360505
Wafer taping apparatus and method Mar 20, 2019 Issued
Array ( [id] => 16332297 [patent_doc_number] => 20200303263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => STACKED VERTICAL FIELD-EFFECT TRANSISTORS WITH SACRIFICIAL LAYER PATTERNING [patent_app_type] => utility [patent_app_number] => 16/360353 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360353
Stacked vertical field-effect transistors with sacrificial layer patterning Mar 20, 2019 Issued
Array ( [id] => 16789152 [patent_doc_number] => 10991590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Etching method and plating solution [patent_app_type] => utility [patent_app_number] => 16/359427 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6982 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359427 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/359427
Etching method and plating solution Mar 19, 2019 Issued
Array ( [id] => 16479563 [patent_doc_number] => 10854517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Methods of manufacturing semiconductor chip [patent_app_type] => utility [patent_app_number] => 16/359440 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/359440
Methods of manufacturing semiconductor chip Mar 19, 2019 Issued
Array ( [id] => 15217961 [patent_doc_number] => 20190371667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Method for Dicing Die Attach Film [patent_app_type] => utility [patent_app_number] => 16/358163 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358163 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358163
Method for Dicing Die Attach Film Mar 18, 2019 Abandoned
Array ( [id] => 16609417 [patent_doc_number] => 10910433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Pixelated LED array with optical elements [patent_app_type] => utility [patent_app_number] => 16/358085 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2890 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358085
Pixelated LED array with optical elements Mar 18, 2019 Issued
Array ( [id] => 18548195 [patent_doc_number] => 11721554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Stress compensation for wafer to wafer bonding [patent_app_type] => utility [patent_app_number] => 16/356402 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 10679 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356402 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356402
Stress compensation for wafer to wafer bonding Mar 17, 2019 Issued
Array ( [id] => 14509747 [patent_doc_number] => 20190198528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Integrated Structures [patent_app_type] => utility [patent_app_number] => 16/290169 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16290169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/290169
Integrated structures Feb 28, 2019 Issued
Array ( [id] => 16286181 [patent_doc_number] => 20200279783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => PROCESS CONTROL OF SEMICONDUCTOR FABRICATION BASED ON LINKAGE BETWEEN DIFFERENT FABRICATION STEPS [patent_app_type] => utility [patent_app_number] => 16/288152 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288152
PROCESS CONTROL OF SEMICONDUCTOR FABRICATION BASED ON LINKAGE BETWEEN DIFFERENT FABRICATION STEPS Feb 27, 2019 Abandoned
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