Search

Patricia D Valenzuela

Examiner (ID: 1976)

Most Active Art Unit
2819
Art Unit(s)
2892, 2812, 2819
Total Applications
682
Issued Applications
540
Pending Applications
71
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15733277 [patent_doc_number] => 10615072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method [patent_app_type] => utility [patent_app_number] => 15/967449 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7681 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967449
Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method Apr 29, 2018 Issued
Array ( [id] => 16264780 [patent_doc_number] => 10756228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Optical sensor and method of manufacture [patent_app_type] => utility [patent_app_number] => 15/967242 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3510 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967242
Optical sensor and method of manufacture Apr 29, 2018 Issued
Array ( [id] => 14738497 [patent_doc_number] => 10388658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-20 [patent_title] => Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors [patent_app_type] => utility [patent_app_number] => 15/965632 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 6140 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/965632
Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors Apr 26, 2018 Issued
Array ( [id] => 13392845 [patent_doc_number] => 20180247965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => DIELECTRIC MIRROR BASED MULTISPECTRAL FILTER ARRAY [patent_app_type] => utility [patent_app_number] => 15/964395 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964395
Dielectric mirror based multispectral filter array Apr 26, 2018 Issued
Array ( [id] => 13378281 [patent_doc_number] => 20180240682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => ATOMIC LAYER ETCH OF TUNGSTEN FOR ENHANCED TUNGSTEN DEPOSITION FILL [patent_app_type] => utility [patent_app_number] => 15/954509 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/954509
ATOMIC LAYER ETCH OF TUNGSTEN FOR ENHANCED TUNGSTEN DEPOSITION FILL Apr 15, 2018 Abandoned
Array ( [id] => 13435047 [patent_doc_number] => 20180269066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Techniques and systems for continuous-flow plasma enhanced atomic layer deposition (PEALD) [patent_app_type] => utility [patent_app_number] => 15/950330 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950330 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950330
Techniques and systems for continuous-flow plasma enhanced atomic layer deposition (PEALD) Apr 10, 2018 Issued
Array ( [id] => 13435049 [patent_doc_number] => 20180269067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Techniques and systems for continuous-flow plasma enhanced atomic layer deposition (PEALD) [patent_app_type] => utility [patent_app_number] => 15/950391 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950391 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950391
Techniques and systems for continuous-flow plasma enhanced atomic layer deposition (PEALD) Apr 10, 2018 Issued
Array ( [id] => 17757057 [patent_doc_number] => 11397348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Array substrate having convex component, method for fabricating the same, liquid crystal display panel, and display device [patent_app_type] => utility [patent_app_number] => 16/300255 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3589 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16300255 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/300255
Array substrate having convex component, method for fabricating the same, liquid crystal display panel, and display device Mar 20, 2018 Issued
Array ( [id] => 16536734 [patent_doc_number] => 10879349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Method for manufacturing semiconductor device and edge termination structure of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/920246 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7515 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920246 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920246
Method for manufacturing semiconductor device and edge termination structure of semiconductor device Mar 12, 2018 Issued
Array ( [id] => 12918598 [patent_doc_number] => 20180198042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 15/917001 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15917001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/917001
Display apparatus Mar 8, 2018 Issued
Array ( [id] => 15286307 [patent_doc_number] => 10515823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Via connection to a partially filled trench [patent_app_type] => utility [patent_app_number] => 15/912177 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 5547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912177 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912177
Via connection to a partially filled trench Mar 4, 2018 Issued
Array ( [id] => 12897136 [patent_doc_number] => 20180190887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => LIGHT EMITTING DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/908779 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/908779
LIGHT EMITTING DEVICE STRUCTURE Feb 27, 2018 Abandoned
Array ( [id] => 12872581 [patent_doc_number] => 20180182702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPACITANCE INTERCONNECTS BY ALTERNATING RECESSED TRENCHES [patent_app_type] => utility [patent_app_number] => 15/903304 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903304
Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Feb 22, 2018 Issued
Array ( [id] => 14889283 [patent_doc_number] => 10424693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Semiconductor light emitting element having first semiconductor layer and holes through second semiconductor layer to expose the first semiconductor layer [patent_app_type] => utility [patent_app_number] => 15/892298 [patent_app_country] => US [patent_app_date] => 2018-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5388 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892298 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/892298
Semiconductor light emitting element having first semiconductor layer and holes through second semiconductor layer to expose the first semiconductor layer Feb 7, 2018 Issued
Array ( [id] => 13799543 [patent_doc_number] => 20190013310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => DUAL FIN SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE [patent_app_type] => utility [patent_app_number] => 15/883306 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883306
Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device Jan 29, 2018 Issued
Array ( [id] => 15200247 [patent_doc_number] => 10497625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Method and apparatus of multi threshold voltage CMOS [patent_app_type] => utility [patent_app_number] => 15/880512 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 37 [patent_no_of_words] => 9928 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880512
Method and apparatus of multi threshold voltage CMOS Jan 24, 2018 Issued
Array ( [id] => 15519507 [patent_doc_number] => 10566352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Array substrate and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/749127 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/749127
Array substrate and manufacturing method thereof Jan 3, 2018 Issued
Array ( [id] => 14350917 [patent_doc_number] => 20190157431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => BACK-CHANNEL-ETCHED TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/749101 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/749101
Back-channel-etched TFT substrate and manufacturing method thereof Dec 19, 2017 Issued
Array ( [id] => 12779431 [patent_doc_number] => 20180151645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/824715 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824715
Organic light emitting display device having a reflective barrier and method of manufacturing the same Nov 27, 2017 Issued
Array ( [id] => 12243233 [patent_doc_number] => 20180076096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'CMOS DEVICE WITH DECREASED LEAKAGE CURRENT AND METHOD MAKING SAME' [patent_app_type] => utility [patent_app_number] => 15/818920 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2725 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818920 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818920
CMOS device with decreased leakage current and method making same Nov 20, 2017 Issued
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