Search

Patricia D Valenzuela

Examiner (ID: 1976)

Most Active Art Unit
2819
Art Unit(s)
2892, 2812, 2819
Total Applications
682
Issued Applications
540
Pending Applications
71
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12773950 [patent_doc_number] => 20180149818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 15/819829 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819829
Semiconductor module Nov 20, 2017 Issued
Array ( [id] => 13335205 [patent_doc_number] => 20180219140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/820270 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820270
LIGHT EMITTING DEVICE Nov 20, 2017 Abandoned
Array ( [id] => 12759043 [patent_doc_number] => 20180144849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => TWO-DIMENSIONAL MATERIALS INTEGRATED WITH MULTIFERROIC LAYERS [patent_app_type] => utility [patent_app_number] => 15/819929 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819929 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819929
Two-dimensional materials integrated with multiferroic layers Nov 20, 2017 Issued
Array ( [id] => 17092000 [patent_doc_number] => 11120190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level [patent_app_type] => utility [patent_app_number] => 15/819879 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819879
Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level Nov 20, 2017 Issued
Array ( [id] => 12760009 [patent_doc_number] => 20180145171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Field Effect Transistor (FET) or Other Semiconductor Device with Front-Side Source and Drain Contacts [patent_app_type] => utility [patent_app_number] => 15/819874 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819874
Field Effect Transistor (FET) or Other Semiconductor Device with Front-Side Source and Drain Contacts Nov 20, 2017 Abandoned
Array ( [id] => 15760333 [patent_doc_number] => 10622294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly [patent_app_type] => utility [patent_app_number] => 15/817787 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817787 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817787
Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly Nov 19, 2017 Issued
Array ( [id] => 15906559 [patent_doc_number] => 20200152800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => CMOS INVERTER AND ARRAY SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/743990 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743990 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/743990
CMOS INVERTER AND ARRAY SUBSTRATE Nov 14, 2017 Abandoned
Array ( [id] => 14317803 [patent_doc_number] => 20190148605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => LIGHT EMITTING DEVICES INCLUDING NARROWBAND CONVERTERS FOR OUTDOOR LIGHTING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/809353 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809353
Light emitting devices including narrowband converters for outdoor lighting applications Nov 9, 2017 Issued
Array ( [id] => 15308683 [patent_doc_number] => 10519031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Encapsulations for mems sense elements and wire bonds [patent_app_type] => utility [patent_app_number] => 15/809368 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3810 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809368
Encapsulations for mems sense elements and wire bonds Nov 9, 2017 Issued
Array ( [id] => 12759442 [patent_doc_number] => 20180144982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/809280 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809280
SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES Nov 9, 2017 Abandoned
Array ( [id] => 13921577 [patent_doc_number] => 10204913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 15/799424 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11662 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799424 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799424
Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof Oct 30, 2017 Issued
Array ( [id] => 16035045 [patent_doc_number] => 10679955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Semiconductor package with heat-dissipating structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/788189 [patent_app_country] => US [patent_app_date] => 2017-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7486 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/788189
Semiconductor package with heat-dissipating structure and method of manufacturing the same Oct 18, 2017 Issued
Array ( [id] => 12162506 [patent_doc_number] => 20180033772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A RIB STRUCTURE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 15/730256 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6224 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730256
SEMICONDUCTOR DEVICE HAVING A RIB STRUCTURE AND MANUFACTURING METHOD OF THE SAME Oct 10, 2017 Abandoned
Array ( [id] => 12260446 [patent_doc_number] => 20180079642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'MICROSCALE METALLIC CNT TEMPLATED DEVICES AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 15/723004 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723004 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723004
Microscale metallic CNT templated devices and related methods Oct 1, 2017 Issued
Array ( [id] => 13288969 [patent_doc_number] => 10155659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Vacuum sealed MEMS and CMOS package [patent_app_type] => utility [patent_app_number] => 15/722214 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722214
Vacuum sealed MEMS and CMOS package Oct 1, 2017 Issued
Array ( [id] => 14351237 [patent_doc_number] => 20190157591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => THIN FILM TRANSISTOR AND METHOD FOR FORMING THE SAME, ARRAY BASEPLATE, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/758970 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15758970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/758970
THIN FILM TRANSISTOR AND METHOD FOR FORMING THE SAME, ARRAY BASEPLATE, AND DISPLAY DEVICE Sep 12, 2017 Abandoned
Array ( [id] => 14267981 [patent_doc_number] => 10283563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Resistive memory cell having a compact structure [patent_app_type] => utility [patent_app_number] => 15/694463 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694463
Resistive memory cell having a compact structure Aug 31, 2017 Issued
Array ( [id] => 12631806 [patent_doc_number] => 20180102432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => VERTICAL VACUUM CHANNEL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/693938 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693938
Vertical vacuum channel transistor Aug 31, 2017 Issued
Array ( [id] => 12631809 [patent_doc_number] => 20180102433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => VERTICAL VACUUM CHANNEL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/693952 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693952
Vertical vacuum channel transistor Aug 31, 2017 Issued
Array ( [id] => 15733275 [patent_doc_number] => 10615071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method [patent_app_type] => utility [patent_app_number] => 15/664157 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7666 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15664157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/664157
Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method Jul 30, 2017 Issued
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