Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17173823 [patent_doc_number] => 20210327494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => HARDWARE-ASSISTED DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW MERGING [patent_app_type] => utility [patent_app_number] => 17/025157 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025157
Hardware-assisted dynamic random access memory (DRAM) row merging Sep 17, 2020 Issued
Array ( [id] => 17346827 [patent_doc_number] => 20220013158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => MAGNETORESISTIVE RANDOM ACCESS MEMORY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/023599 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023599
Magnetoresistive random access memory and operating method thereof Sep 16, 2020 Issued
Array ( [id] => 17878370 [patent_doc_number] => 11450391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Multi-tier threshold voltage offset bin calibration [patent_app_type] => utility [patent_app_number] => 16/948359 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11279 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948359 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948359
Multi-tier threshold voltage offset bin calibration Sep 14, 2020 Issued
Array ( [id] => 16560114 [patent_doc_number] => 20210005263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => OPERATIONS ON MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/019582 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019582
Operations on memory cells Sep 13, 2020 Issued
Array ( [id] => 18480991 [patent_doc_number] => 11694742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Apparatuses and methods for internal voltage generating circuits [patent_app_type] => utility [patent_app_number] => 17/018339 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10818 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018339 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018339
Apparatuses and methods for internal voltage generating circuits Sep 10, 2020 Issued
Array ( [id] => 17253852 [patent_doc_number] => 11189348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/009389 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009389
Semiconductor memory device Aug 31, 2020 Issued
Array ( [id] => 17121915 [patent_doc_number] => 11133055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Electronic device to perform read operation and mode register read operation [patent_app_type] => utility [patent_app_number] => 17/009413 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009413
Electronic device to perform read operation and mode register read operation Aug 31, 2020 Issued
Array ( [id] => 17870395 [patent_doc_number] => 20220293132 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2022-09-15 [patent_title] => SCALABLE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/008208 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008208
Scalable storage device Aug 30, 2020 Issued
Array ( [id] => 17870395 [patent_doc_number] => 20220293132 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2022-09-15 [patent_title] => SCALABLE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/008208 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008208
Scalable storage device Aug 30, 2020 Issued
Array ( [id] => 16794862 [patent_doc_number] => 20210124679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => MEMORY DEVICE, METHOD OF OPERATING MEMORY DEVICE, AND COMPUTER SYSTEM INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/007501 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007501
Memory device, method of operating memory device, and computer system including memory device Aug 30, 2020 Issued
Array ( [id] => 16936091 [patent_doc_number] => 20210201980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/006238 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006238
Semiconductor storage device Aug 27, 2020 Issued
Array ( [id] => 17130059 [patent_doc_number] => 20210304828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/004983 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004983
Semiconductor memory device and method of operating the semiconductor memory device Aug 26, 2020 Issued
Array ( [id] => 17353006 [patent_doc_number] => 11227650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Delay circuitry with reduced instabilities [patent_app_type] => utility [patent_app_number] => 17/002398 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002398
Delay circuitry with reduced instabilities Aug 24, 2020 Issued
Array ( [id] => 18856295 [patent_doc_number] => 11853880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => SRAM architecture for convolutional neural network application [patent_app_type] => utility [patent_app_number] => 17/001947 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 12974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001947
SRAM architecture for convolutional neural network application Aug 24, 2020 Issued
Array ( [id] => 17529690 [patent_doc_number] => 11302388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Decoding for pseudo-triple-port SRAM [patent_app_type] => utility [patent_app_number] => 17/002010 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7721 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002010
Decoding for pseudo-triple-port SRAM Aug 24, 2020 Issued
Array ( [id] => 17098765 [patent_doc_number] => 20210286556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MEMORY SYSTEM FOR READ OPERATION AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/998530 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998530
Memory system for read operation and operating method thereof Aug 19, 2020 Issued
Array ( [id] => 17652464 [patent_doc_number] => 11355200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Hybrid routine for a memory device [patent_app_type] => utility [patent_app_number] => 16/996363 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 16097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/996363
Hybrid routine for a memory device Aug 17, 2020 Issued
Array ( [id] => 17795331 [patent_doc_number] => 20220254423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => ONE DIRECTION-SHIFT REGISTER ALIASING TABLE CIRCUIT SUITABLE FOR USE IN MICROPROCESSORS [patent_app_type] => utility [patent_app_number] => 17/629656 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17629656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/629656
One direction-shift register aliasing table circuit suitable for use in microprocessors Aug 4, 2020 Issued
Array ( [id] => 16552802 [patent_doc_number] => 10885966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-05 [patent_title] => Method and circuit for protecting a DRAM memory device from the row hammer effect [patent_app_type] => utility [patent_app_number] => 16/984212 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7904 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984212
Method and circuit for protecting a DRAM memory device from the row hammer effect Aug 3, 2020 Issued
Array ( [id] => 17353213 [patent_doc_number] => 11227860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/942854 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942854
Memory device Jul 29, 2020 Issued
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