Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16447984 [patent_doc_number] => 10839915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Bitline boost for nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/454468 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14433 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16454468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/454468
Bitline boost for nonvolatile memory Jun 26, 2019 Issued
Array ( [id] => 16423687 [patent_doc_number] => 20200348885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => ELECTRONIC APPARATUS AND METHOD OF MANAGING READ LEVELS OF FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 16/438386 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/438386
Electronic apparatus and method of managing read levels of flash memory Jun 10, 2019 Issued
Array ( [id] => 16591634 [patent_doc_number] => 10900890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Method and device for evaluating the quality of a component produced by means of an additive laser sintering and/or laser melting method [patent_app_type] => utility [patent_app_number] => 16/436456 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4002 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/436456
Method and device for evaluating the quality of a component produced by means of an additive laser sintering and/or laser melting method Jun 9, 2019 Issued
Array ( [id] => 17543917 [patent_doc_number] => 11309049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Direct memory access using JTAG cell addressing [patent_app_type] => utility [patent_app_number] => 16/624665 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7223 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16624665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/624665
Direct memory access using JTAG cell addressing May 30, 2019 Issued
Array ( [id] => 17573949 [patent_doc_number] => 11322223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => JTAG based architecture allowing multi-core operation [patent_app_type] => utility [patent_app_number] => 16/625455 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11197 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625455 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625455
JTAG based architecture allowing multi-core operation May 30, 2019 Issued
Array ( [id] => 17032540 [patent_doc_number] => 11094357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Memory devices with user-defined tagging mechanism [patent_app_type] => utility [patent_app_number] => 16/405072 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405072
Memory devices with user-defined tagging mechanism May 6, 2019 Issued
Array ( [id] => 16566624 [patent_doc_number] => 10891998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Memory device operating based on a write current for a given operation condition and a method of driving the write current [patent_app_type] => utility [patent_app_number] => 16/401236 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11161 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401236
Memory device operating based on a write current for a given operation condition and a method of driving the write current May 1, 2019 Issued
Array ( [id] => 16424828 [patent_doc_number] => 20200350026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => PEAK CURRENT MANAGEMENT IN A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/400398 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400398
Peak current management in a memory array Apr 30, 2019 Issued
Array ( [id] => 15938525 [patent_doc_number] => 20200160896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/400680 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400680
Semiconductor devices Apr 30, 2019 Issued
Array ( [id] => 15806933 [patent_doc_number] => 20200126609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MEMORY MODULES, MEMORY SYSTEMS, AND METHODS OF OPERATING MEMORY MODULES [patent_app_type] => utility [patent_app_number] => 16/390460 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390460
Memory modules, memory systems, and methods of operating memory modules Apr 21, 2019 Issued
Array ( [id] => 16818563 [patent_doc_number] => 11003389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Memory device including memory chips and operation method thereof [patent_app_type] => utility [patent_app_number] => 16/384702 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7727 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384702
Memory device including memory chips and operation method thereof Apr 14, 2019 Issued
Array ( [id] => 16372178 [patent_doc_number] => 10803944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Architecture for 3-D NAND memory [patent_app_type] => utility [patent_app_number] => 16/378090 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378090 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378090
Architecture for 3-D NAND memory Apr 7, 2019 Issued
Array ( [id] => 16819680 [patent_doc_number] => 11004517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Storage device including nonvolatile memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/356182 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11837 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356182
Storage device including nonvolatile memory device and operating method thereof Mar 17, 2019 Issued
Array ( [id] => 16249254 [patent_doc_number] => 10748628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Read level tracking and optimization [patent_app_type] => utility [patent_app_number] => 16/354039 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354039
Read level tracking and optimization Mar 13, 2019 Issued
Array ( [id] => 14784407 [patent_doc_number] => 20190267101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SERIAL INTERFACE CIRCUIT, SEMICONDUCTOR DEVICE AND SERIAL-PARALLEL CONVERSION METHOD [patent_app_type] => utility [patent_app_number] => 16/283848 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283848
Serial interface circuit, semiconductor device and serial-parallel conversion method Feb 24, 2019 Issued
Array ( [id] => 16210521 [patent_doc_number] => 20200243511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HIGH VOLTAGE PROTECTION FOR HIGH-SPEED DATA INTERFACE [patent_app_type] => utility [patent_app_number] => 16/256945 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256945 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256945
High voltage protection for high-speed data interface Jan 23, 2019 Issued
Array ( [id] => 14284647 [patent_doc_number] => 20190139608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/242489 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242489 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242489
Semiconductor memory device Jan 7, 2019 Issued
Array ( [id] => 14221347 [patent_doc_number] => 20190123058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS [patent_app_type] => utility [patent_app_number] => 16/228574 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228574 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228574
Memory device including pass transistors in memory tiers Dec 19, 2018 Issued
Array ( [id] => 16873292 [patent_doc_number] => 20210166759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR CIRCUIT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/768879 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16768879 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/768879
Semiconductor circuit and semiconductor circuit system Dec 3, 2018 Issued
Array ( [id] => 16323985 [patent_doc_number] => 10783955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Memory circuit having shared word line [patent_app_type] => utility [patent_app_number] => 16/207030 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7565 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207030
Memory circuit having shared word line Nov 29, 2018 Issued
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