Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15199889 [patent_doc_number] => 10497446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Memory system controlling data erase for nonvolatile memory and control method for erasing data [patent_app_type] => utility [patent_app_number] => 15/890427 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 13690 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890427
Memory system controlling data erase for nonvolatile memory and control method for erasing data Feb 6, 2018 Issued
Array ( [id] => 15984249 [patent_doc_number] => 10672459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Transition coupling circuitry for memory applications [patent_app_type] => utility [patent_app_number] => 15/891212 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/891212
Transition coupling circuitry for memory applications Feb 6, 2018 Issued
Array ( [id] => 15233683 [patent_doc_number] => 10504570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Semiconductor device and timing calibration method [patent_app_type] => utility [patent_app_number] => 15/889928 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 11836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889928 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889928
Semiconductor device and timing calibration method Feb 5, 2018 Issued
Array ( [id] => 14952585 [patent_doc_number] => 10437557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Determination of a match between data values stored by several arrays [patent_app_type] => utility [patent_app_number] => 15/885316 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7295 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885316
Determination of a match between data values stored by several arrays Jan 30, 2018 Issued
Array ( [id] => 12775786 [patent_doc_number] => 20180150430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => INTEGRATED CIRCUIT FOR OPERATING ON A BUS, AND METHOD FOR OPERATING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/879854 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879854 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879854
Integrated circuit for operating on a bus, and method for operating the integrated circuit Jan 24, 2018 Issued
Array ( [id] => 15788651 [patent_doc_number] => 10628049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Systems and methods for on-die control of memory command, timing, and/or control signals [patent_app_type] => utility [patent_app_number] => 15/870390 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 25583 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870390
Systems and methods for on-die control of memory command, timing, and/or control signals Jan 11, 2018 Issued
Array ( [id] => 16494040 [patent_doc_number] => 10860080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Storage device, semiconductor device, electronic component, and electronic device [patent_app_type] => utility [patent_app_number] => 16/476642 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 42 [patent_no_of_words] => 15240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476642 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/476642
Storage device, semiconductor device, electronic component, and electronic device Jan 8, 2018 Issued
Array ( [id] => 12712303 [patent_doc_number] => 20180129267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHODS OF USE [patent_app_type] => utility [patent_app_number] => 15/863155 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863155 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863155
Memory interface with adjustable voltage and termination and methods of use Jan 4, 2018 Issued
Array ( [id] => 14919887 [patent_doc_number] => 10431270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Apparatuses for modulating threshold voltages of memory cells [patent_app_type] => utility [patent_app_number] => 15/859029 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6588 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859029
Apparatuses for modulating threshold voltages of memory cells Dec 28, 2017 Issued
Array ( [id] => 15919623 [patent_doc_number] => 10657051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/841640 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841640
Memory device and operation method thereof Dec 13, 2017 Issued
Array ( [id] => 14109569 [patent_doc_number] => 20190096460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => MEMORY HOLD MARGIN CHARACTERIZATION AND CORRECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/842460 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842460
Memory hold margin characterization and correction circuit Dec 13, 2017 Issued
Array ( [id] => 14366457 [patent_doc_number] => 10304540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/841688 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3019 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841688 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841688
Memory device and operation method thereof Dec 13, 2017 Issued
Array ( [id] => 14397283 [patent_doc_number] => 10311929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Resistance change memory [patent_app_type] => utility [patent_app_number] => 15/835988 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 7073 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835988
Resistance change memory Dec 7, 2017 Issued
Array ( [id] => 13876049 [patent_doc_number] => 20190034365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MEASUREMENT AND OPTIMIZATION OF COMMAND SIGNAL TIMING MARGINS [patent_app_type] => utility [patent_app_number] => 15/829524 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829524 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829524
Measurement and optimization of command signal timing margins Nov 30, 2017 Issued
Array ( [id] => 14381375 [patent_doc_number] => 20190164600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => COMPARING INPUT DATA TO STORED DATA [patent_app_type] => utility [patent_app_number] => 15/827019 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/827019
Comparing input data to stored data Nov 29, 2017 Issued
Array ( [id] => 14768675 [patent_doc_number] => 10395738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Operations on memory cells [patent_app_type] => utility [patent_app_number] => 15/827119 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 20170 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/827119
Operations on memory cells Nov 29, 2017 Issued
Array ( [id] => 14381369 [patent_doc_number] => 20190164597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SYNAPTIC CROSSBAR MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/826654 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826654
Synaptic crossbar memory array Nov 28, 2017 Issued
Array ( [id] => 16249256 [patent_doc_number] => 10748630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks [patent_app_type] => utility [patent_app_number] => 15/826345 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 51 [patent_no_of_words] => 11188 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826345 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826345
High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks Nov 28, 2017 Issued
Array ( [id] => 12263542 [patent_doc_number] => 20180082738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'Signal Processing Circuit' [patent_app_type] => utility [patent_app_number] => 15/822850 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10769 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822850
Signal processing circuit Nov 26, 2017 Issued
Array ( [id] => 16416685 [patent_doc_number] => 10824580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/815048 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10329 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815048 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/815048
Semiconductor device Nov 15, 2017 Issued
Menu