Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18874412 [patent_doc_number] => 11862233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => System and method for detecting mismatch of sense amplifier [patent_app_type] => utility [patent_app_number] => 17/664058 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7345 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664058
System and method for detecting mismatch of sense amplifier May 18, 2022 Issued
Array ( [id] => 19093731 [patent_doc_number] => 11955195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semiconductor memory device with defect detection capability [patent_app_type] => utility [patent_app_number] => 17/748441 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 62 [patent_no_of_words] => 14386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748441
Semiconductor memory device with defect detection capability May 18, 2022 Issued
Array ( [id] => 17840490 [patent_doc_number] => 20220277796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => HYBRID ROUTINE FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/747516 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747516
Hybrid routine for a memory device May 17, 2022 Issued
Array ( [id] => 18757233 [patent_doc_number] => 20230360691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => APPARATUSES FOR SENSE AMPLIFIER VOLTAGE CONTROL [patent_app_type] => utility [patent_app_number] => 17/737999 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737999
Apparatuses for sense amplifier voltage control May 4, 2022 Issued
Array ( [id] => 19123395 [patent_doc_number] => 11967389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Semiconductor apparatus related to a test function [patent_app_type] => utility [patent_app_number] => 17/737268 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6336 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737268
Semiconductor apparatus related to a test function May 4, 2022 Issued
Array ( [id] => 18243648 [patent_doc_number] => 20230075959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SRAM DESIGN FOR ENERGY EFFICIENT SEQUENTIAL ACCESS [patent_app_type] => utility [patent_app_number] => 17/737820 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737820
SRAM design for energy efficient sequential access May 4, 2022 Issued
Array ( [id] => 19399484 [patent_doc_number] => 12073869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Compute in memory system [patent_app_type] => utility [patent_app_number] => 17/734701 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734701
Compute in memory system May 1, 2022 Issued
Array ( [id] => 17795346 [patent_doc_number] => 20220254438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION [patent_app_type] => utility [patent_app_number] => 17/734747 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734747
JTAG based architecture allowing multi-core operation May 1, 2022 Issued
Array ( [id] => 18039719 [patent_doc_number] => 20220383936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY STRUCTURE AND MEMORY LAYOUT [patent_app_type] => utility [patent_app_number] => 17/661326 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661326
Memory structure and memory layout Apr 28, 2022 Issued
Array ( [id] => 18729090 [patent_doc_number] => 20230343385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => IR DROP COMPENSATION FOR SENSING MEMORY [patent_app_type] => utility [patent_app_number] => 17/725712 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725712
IR drop compensation for sensing memory Apr 20, 2022 Issued
Array ( [id] => 19228600 [patent_doc_number] => 12008237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Memory bit cell with homogeneous layout pattern of base layers for high density memory macros [patent_app_type] => utility [patent_app_number] => 17/724123 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724123
Memory bit cell with homogeneous layout pattern of base layers for high density memory macros Apr 18, 2022 Issued
Array ( [id] => 18198344 [patent_doc_number] => 20230051863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MEMORY DEVICE FOR WAFER-ON-WAFER FORMED MEMORY AND LOGIC [patent_app_type] => utility [patent_app_number] => 17/712935 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712935
Memory device for wafer-on-wafer formed memory and logic Apr 3, 2022 Issued
Array ( [id] => 17723160 [patent_doc_number] => 20220215882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => TERNARY CONTENT ADDRESSABLE MEMORY BASED ON MEMORY DIODE [patent_app_type] => utility [patent_app_number] => 17/704041 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704041
Ternary content addressable memory based on memory diode Mar 24, 2022 Issued
Array ( [id] => 17900492 [patent_doc_number] => 20220310154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER [patent_app_type] => utility [patent_app_number] => 17/685067 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685067
Memory device transmitting and receiving data at high speed and low power Mar 1, 2022 Issued
Array ( [id] => 18346865 [patent_doc_number] => 20230134975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/684951 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/684951
Memory device Mar 1, 2022 Issued
Array ( [id] => 17854903 [patent_doc_number] => 20220284946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DRAM DEVICE AND ODT RESISTOR VALUE ADJUSTMENT METHOD AND COMPUTER PROGRAM FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/678500 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/678500
DRAM device and ODT resistor value adjustment method and computer program for the same Feb 22, 2022 Issued
Array ( [id] => 18179081 [patent_doc_number] => 20230039810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => REFRESH COUNTER CIRCUIT, REFRESH COUNTING METHOD AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/669585 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669585
Refresh counter circuit, refresh counting method and semiconductor memory Feb 10, 2022 Issued
Array ( [id] => 18237856 [patent_doc_number] => 20230070166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/665300 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665300
Semiconductor memory device and operating method of the semiconductor memory device Feb 3, 2022 Issued
Array ( [id] => 19444260 [patent_doc_number] => 12094546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Non-volatile memory with zone based program speed adjustment [patent_app_type] => utility [patent_app_number] => 17/589789 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 21921 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589789 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589789
Non-volatile memory with zone based program speed adjustment Jan 30, 2022 Issued
Array ( [id] => 18874415 [patent_doc_number] => 11862236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Memory component for deployment in a dynamic stripe width memory system [patent_app_type] => utility [patent_app_number] => 17/588561 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588561
Memory component for deployment in a dynamic stripe width memory system Jan 30, 2022 Issued
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