Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9733313 [patent_doc_number] => 20140269022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'THREE-DIMENSIONAL (3D) MEMORY CELL SEPARATION AMONG 3D INTEGRATED CIRCUIT (IC) TIERS, AND RELATED 3D INTEGRATED CIRCUITS (3DICS), 3DIC PROCESSOR CORES, AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/939274 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4795 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939274 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/939274
Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods Jul 10, 2013 Issued
Array ( [id] => 9221622 [patent_doc_number] => 20140016397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND WRITE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/939324 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939324 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/939324
NONVOLATILE MEMORY DEVICE AND WRITE METHOD THEREOF Jul 10, 2013 Abandoned
Array ( [id] => 9733303 [patent_doc_number] => 20140269012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'GROUND-REFERENCED SINGLE-ENDED SYSTEM-ON-PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/938161 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11209 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13938161 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/938161
Ground-referenced single-ended system-on-package Jul 8, 2013 Issued
Array ( [id] => 9240701 [patent_doc_number] => 08605498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Reliable set operation for phase-change memory cell' [patent_app_type] => utility [patent_app_number] => 13/903261 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10198 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903261 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903261
Reliable set operation for phase-change memory cell May 27, 2013 Issued
Array ( [id] => 9733301 [patent_doc_number] => 20140269010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 13/890899 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11715 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/890899
Ground-referenced single-ended memory interconnect May 8, 2013 Issued
Array ( [id] => 10138263 [patent_doc_number] => 09171584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines' [patent_app_type] => utility [patent_app_number] => 13/886874 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 24916 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13886874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/886874
Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines May 2, 2013 Issued
Array ( [id] => 9033049 [patent_doc_number] => 20130235687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'Asymmetric Sense Amplifier Design' [patent_app_type] => utility [patent_app_number] => 13/886120 [patent_app_country] => US [patent_app_date] => 2013-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13886120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/886120
Asymmetric sense amplifier design May 1, 2013 Issued
Array ( [id] => 9119835 [patent_doc_number] => 20130286757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/864476 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8061 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13864476 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/864476
Semiconductor device and driving method thereof Apr 16, 2013 Issued
Array ( [id] => 10904487 [patent_doc_number] => 20140307500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL' [patent_app_type] => utility [patent_app_number] => 13/863208 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13863208 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/863208
Integrated circuit memory device with read-disturb control Apr 14, 2013 Issued
Array ( [id] => 9684307 [patent_doc_number] => 20140241070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'REFERENCE AND SENSING WITH BIT LINE STEPPING METHOD OF MEMORY' [patent_app_type] => utility [patent_app_number] => 13/861970 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861970 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/861970
Reference and sensing with bit line stepping method of memory Apr 11, 2013 Issued
Array ( [id] => 9092740 [patent_doc_number] => 20130272051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/862290 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6094 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/862290
Non-volatile memory and semiconductor device Apr 11, 2013 Issued
Array ( [id] => 9092757 [patent_doc_number] => 20130272068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'MANAGING OF THE ERASING OF OPERATIVE PAGES OF A FLASH MEMORY DEVICE THROUGH SERVICE PAGES' [patent_app_type] => utility [patent_app_number] => 13/860056 [patent_app_country] => US [patent_app_date] => 2013-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6475 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860056 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/860056
Managing of the erasing of operative pages of a flash memory device through service pages Apr 9, 2013 Issued
Array ( [id] => 9080284 [patent_doc_number] => 20130265814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'MAGNETIC RAMDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 13/859132 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5522 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859132
Magnetic ramdom access memory Apr 8, 2013 Issued
Array ( [id] => 10138317 [patent_doc_number] => 09171638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Nonvolatile storage device, integrated circuit device, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/857418 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857418
Nonvolatile storage device, integrated circuit device, and electronic apparatus Apr 4, 2013 Issued
Array ( [id] => 10525352 [patent_doc_number] => 09251870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Ground-referenced single-ended memory interconnect' [patent_app_type] => utility [patent_app_number] => 13/857099 [patent_app_country] => US [patent_app_date] => 2013-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10380 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857099
Ground-referenced single-ended memory interconnect Apr 3, 2013 Issued
Array ( [id] => 10003853 [patent_doc_number] => 09047951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/841222 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7669 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/841222
Semiconductor memory device Mar 14, 2013 Issued
Array ( [id] => 11346057 [patent_doc_number] => 09530469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/843306 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10565 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/843306
Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof Mar 14, 2013 Issued
Array ( [id] => 10112063 [patent_doc_number] => 09147481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 13/842876 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 15115 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842876 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842876
Semiconductor memory apparatus Mar 14, 2013 Issued
Array ( [id] => 9092756 [patent_doc_number] => 20130272067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'NON-BOOSTING PROGRAM INHIBIT SCHEME IN NAND DESIGN' [patent_app_type] => utility [patent_app_number] => 13/843642 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17639 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843642 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/843642
Non-boosting program inhibit scheme in NAND design Mar 14, 2013 Issued
Array ( [id] => 10112064 [patent_doc_number] => 09147482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Data transmission circuit, memory including the same, and data transmission method' [patent_app_type] => utility [patent_app_number] => 13/843580 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9104 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/843580
Data transmission circuit, memory including the same, and data transmission method Mar 14, 2013 Issued
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