Patricia L Morris

Array ( [id] => 9764115 [patent_doc_number] => 08848451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => '3D semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/526896 [patent_app_country] => US [patent_app_date] => 2012-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13526896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8605246 [patent_doc_number] => 20130010558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof' [patent_app_type] => utility [patent_app_number] => 13/525372 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3512 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13525372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9611667 [patent_doc_number] => 08788856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Control apparatus and method' [patent_app_type] => utility [patent_app_number] => 13/525776 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4293 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13525776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9966285 [patent_doc_number] => 09013908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Control scheme for 3D memory IC' [patent_app_type] => utility [patent_app_number] => 13/524980 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6397 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13524980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9196750 [patent_doc_number] => 20130336065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'ARCHITECTURE FOR 3-D NAND MEMORY' [patent_app_type] => utility [patent_app_number] => 13/524872 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8904 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13524872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10015844 [patent_doc_number] => 09058865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'Multi-level cell operation in silver/amorphous silicon RRAM' [patent_app_type] => utility [patent_app_number] => 13/525096 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13525096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8372445 [patent_doc_number] => 20120221829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD FOR MANAGING A MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/466147 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14365 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8372393 [patent_doc_number] => 20120221782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/466138 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14820 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9415243 [patent_doc_number] => 08699289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Techniques for reducing disturbance in a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/465982 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7551 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8702702 [patent_doc_number] => 08395929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Signal margin improvement for read operations in a cross-point memory array' [patent_app_type] => utility [patent_app_number] => 13/449011 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9751002 [patent_doc_number] => 08842489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Fast-switching word line driver' [patent_app_type] => utility [patent_app_number] => 13/447318 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3434 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9890306 [patent_doc_number] => 08976573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Apparatus for SRAM cells' [patent_app_type] => utility [patent_app_number] => 13/446220 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9705662 [patent_doc_number] => 08830743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Method of operating memory controller, memory controller, memory device and memory system' [patent_app_type] => utility [patent_app_number] => 13/445048 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9942 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8452057 [patent_doc_number] => 20120263003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'DEVICE PERFORMING REFRESH OPERATIONS OF MEMORY AREAS' [patent_app_type] => utility [patent_app_number] => 13/444032 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8417 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9080306 [patent_doc_number] => 20130265836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'WEAK BIT DETECTION IN A MEMORY THROUGH VARIABLE DEVELOPMENT TIME' [patent_app_type] => utility [patent_app_number] => 13/443170 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8636225 [patent_doc_number] => 20130028028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/417494 [patent_app_country] => US [patent_app_date] => 2012-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13417494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9959610 [patent_doc_number] => 09007824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Boosting memory reads' [patent_app_type] => utility [patent_app_number] => 13/415916 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5474 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13415916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8392256 [patent_doc_number] => 20120230097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'DETERMINING CELL-STATE IN PHASE-CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/415012 [patent_app_country] => US [patent_app_date] => 2012-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6415 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13415012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9033022 [patent_doc_number] => 20130235660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'LOCAL SELF-BOOST USING A PLURALITY OF CUT-OFF CELLS ON A SINGLE SIDE OF A STRING OF MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/413762 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3808 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13413762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9470720 [patent_doc_number] => 08724363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Anti-fuse memory ultilizing a coupling channel and operating method thereof' [patent_app_type] => utility [patent_app_number] => 13/413626 [patent_app_country] => US [patent_app_date] => 2012-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6734 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13413626 [rel_patent_id] =>[rel_patent_doc_number] =>)