Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18423680 [patent_doc_number] => 20230178144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => AVERAGE REFERENCE VOLTAGE FOR SENSING MEMORY [patent_app_type] => utility [patent_app_number] => 17/544471 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544471
Average reference voltage for sensing memory Dec 6, 2021 Issued
Array ( [id] => 17630315 [patent_doc_number] => 20220165330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => DOUBLE-PITCH-LAYOUT TECHNIQUES AND APPARATUS THEREOF [patent_app_type] => utility [patent_app_number] => 17/543547 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543547
DOUBLE-PITCH-LAYOUT TECHNIQUES AND APPARATUS THEREOF Dec 5, 2021 Pending
Array ( [id] => 17463430 [patent_doc_number] => 20220076736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => Output Buffer Circuit With Metal Option [patent_app_type] => utility [patent_app_number] => 17/529101 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529101
Output buffer circuit with metal option Nov 16, 2021 Issued
Array ( [id] => 18219337 [patent_doc_number] => 11594283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Non-volatile memory device and memory system including the same and program method thereof [patent_app_type] => utility [patent_app_number] => 17/523385 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 475 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523385
Non-volatile memory device and memory system including the same and program method thereof Nov 9, 2021 Issued
Array ( [id] => 18935218 [patent_doc_number] => 11887656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Memory for improving efficiency of error correction [patent_app_type] => utility [patent_app_number] => 17/523669 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5850 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 482 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523669
Memory for improving efficiency of error correction Nov 9, 2021 Issued
Array ( [id] => 17630317 [patent_doc_number] => 20220165332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/520020 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520020
Semiconductor device Nov 4, 2021 Issued
Array ( [id] => 18704496 [patent_doc_number] => 11791012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Standby circuit dispatch method, apparatus, device and medium [patent_app_type] => utility [patent_app_number] => 17/515776 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9409 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515776
Standby circuit dispatch method, apparatus, device and medium Oct 31, 2021 Issued
Array ( [id] => 17447816 [patent_doc_number] => 20220068321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD AND SYSTEM FOR ADJUSTING MEMORY, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/510453 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510453
Method and system for adjusting memory, and semiconductor device Oct 25, 2021 Issued
Array ( [id] => 17447816 [patent_doc_number] => 20220068321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD AND SYSTEM FOR ADJUSTING MEMORY, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/510453 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510453
Method and system for adjusting memory, and semiconductor device Oct 25, 2021 Issued
Array ( [id] => 17447816 [patent_doc_number] => 20220068321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD AND SYSTEM FOR ADJUSTING MEMORY, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/510453 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510453
Method and system for adjusting memory, and semiconductor device Oct 25, 2021 Issued
Array ( [id] => 17447816 [patent_doc_number] => 20220068321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD AND SYSTEM FOR ADJUSTING MEMORY, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/510453 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510453
Method and system for adjusting memory, and semiconductor device Oct 25, 2021 Issued
Array ( [id] => 18688141 [patent_doc_number] => 11783884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor memory device and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/505284 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8144 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505284
Semiconductor memory device and memory system including the same Oct 18, 2021 Issued
Array ( [id] => 18935253 [patent_doc_number] => 11887691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Temporal memory systems and methods [patent_app_type] => utility [patent_app_number] => 17/492524 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5656 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492524
Temporal memory systems and methods Sep 30, 2021 Issued
Array ( [id] => 18283303 [patent_doc_number] => 20230098775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SELECTING READ REFERENCE VOLTAGE USING HISTORICAL DECODING INFORMATION [patent_app_type] => utility [patent_app_number] => 17/490304 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490304
Selecting read reference voltage using historical decoding information Sep 29, 2021 Issued
Array ( [id] => 18230206 [patent_doc_number] => 20230069200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY DEVICE AND PROGRAM OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/488701 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488701
Memory device and program operation thereof Sep 28, 2021 Issued
Array ( [id] => 18464144 [patent_doc_number] => 11688437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Amplifier offset cancelation [patent_app_type] => utility [patent_app_number] => 17/481867 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481867
Amplifier offset cancelation Sep 21, 2021 Issued
Array ( [id] => 18766735 [patent_doc_number] => 11817142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Refresh circuit and memory [patent_app_type] => utility [patent_app_number] => 17/480342 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6847 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480342
Refresh circuit and memory Sep 20, 2021 Issued
Array ( [id] => 17318526 [patent_doc_number] => 20210407576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => MEMORY BANK AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/447569 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447569
Memory bank and memory Sep 12, 2021 Issued
Array ( [id] => 17477117 [patent_doc_number] => 20220084621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => DEFECT REPAIR CIRCUIT AND DEFECT REPAIR METHOD [patent_app_type] => utility [patent_app_number] => 17/467529 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467529
Defect repair circuit and defect repair method Sep 6, 2021 Issued
Array ( [id] => 17431474 [patent_doc_number] => 20220059183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD AND DEVICE FOR FAIL BIT REPAIRING [patent_app_type] => utility [patent_app_number] => 17/464886 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464886
Method and device for fail bit repairing Sep 1, 2021 Issued
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