Search

Patricia L Morris

Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1203, 1201, 1612, 1209, 1625
Total Applications
3798
Issued Applications
2688
Pending Applications
142
Abandoned Applications
966

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18067982 [patent_doc_number] => 20220399070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => SIGNAL DROP COMPENSATED MEMORY [patent_app_type] => utility [patent_app_number] => 17/343348 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343348
Signal drop compensated memory Jun 8, 2021 Issued
Array ( [id] => 18120344 [patent_doc_number] => 11551742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Temperature compensated memory refresh [patent_app_type] => utility [patent_app_number] => 17/336383 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3800 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336383
Temperature compensated memory refresh Jun 1, 2021 Issued
Array ( [id] => 17599070 [patent_doc_number] => 20220148644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => INTEGRATED CIRCUIT INCLUDING CELL ARRAY WITH WRITE ASSIST CELL [patent_app_type] => utility [patent_app_number] => 17/335509 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335509
Integrated circuit including cell array with write assist cell May 31, 2021 Issued
Array ( [id] => 18190703 [patent_doc_number] => 11581305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => High voltage protection for high-speed data interface [patent_app_type] => utility [patent_app_number] => 17/326231 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6589 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326231
High voltage protection for high-speed data interface May 19, 2021 Issued
Array ( [id] => 17055921 [patent_doc_number] => 20210265355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => Integrated Memory Having Non-Ohmic Devices and Capacitors [patent_app_type] => utility [patent_app_number] => 17/317693 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317693
Integrated Memory Having Non-Ohmic Devices and Capacitors May 10, 2021 Abandoned
Array ( [id] => 18703130 [patent_doc_number] => 11789640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Estimation of read level thresholds using a data structure [patent_app_type] => utility [patent_app_number] => 17/316612 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316612
Estimation of read level thresholds using a data structure May 9, 2021 Issued
Array ( [id] => 17262351 [patent_doc_number] => 20210375336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => ELECTRONIC DEVICE TO PERFORM READ OPERATION AND MODE REGISTER READ OPERATION [patent_app_type] => utility [patent_app_number] => 17/306598 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306598
Electronic device to perform read operation and mode register read operation May 2, 2021 Issued
Array ( [id] => 18482685 [patent_doc_number] => 11696454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Three dimensional memory arrays [patent_app_type] => utility [patent_app_number] => 17/306444 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9728 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306444
Three dimensional memory arrays May 2, 2021 Issued
Array ( [id] => 17025202 [patent_doc_number] => 20210249074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => NONVOLATILE MEMORY APPARATUS FOR PERFORMING A READ OPERATION AND A METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/245870 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245870
Nonvolatile memory apparatus for performing a read operation and a method of operating the same Apr 29, 2021 Issued
Array ( [id] => 17763295 [patent_doc_number] => 20220236907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => DEVICES FOR GENERATING MODE COMMANDS [patent_app_type] => utility [patent_app_number] => 17/240330 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240330 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240330
Devices for generating mode commands Apr 25, 2021 Issued
Array ( [id] => 18415818 [patent_doc_number] => 11670363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Multi-tier memory architecture [patent_app_type] => utility [patent_app_number] => 17/238683 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/238683
Multi-tier memory architecture Apr 22, 2021 Issued
Array ( [id] => 17009236 [patent_doc_number] => 20210240397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => ELECTRONIC APPARATUS AND METHOD OF MANAGING READ LEVELS OF FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/235935 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235935
Electronic apparatus and method of managing read levels of flash memory Apr 20, 2021 Issued
Array ( [id] => 18047714 [patent_doc_number] => 11521672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Semiconductor device and memory system [patent_app_type] => utility [patent_app_number] => 17/230519 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 11916 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/230519
Semiconductor device and memory system Apr 13, 2021 Issued
Array ( [id] => 17216303 [patent_doc_number] => 20210349641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => MEMORY CIRCUIT AND MEMORY REPAIR METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/226518 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17226518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/226518
Memory circuit and memory repair method thereof Apr 8, 2021 Issued
Array ( [id] => 17115326 [patent_doc_number] => 20210295923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/224698 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224698
INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES Apr 6, 2021 Abandoned
Array ( [id] => 17447851 [patent_doc_number] => 20220068356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MULTI-LEVEL SIGNAL RECEIVERS AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/223458 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223458
Multi-level signal receivers and memory systems including the same Apr 5, 2021 Issued
Array ( [id] => 18088382 [patent_doc_number] => 11538521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Adaptive application of voltage pulses to stabilize memory cell voltage levels [patent_app_type] => utility [patent_app_number] => 17/222949 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222949
Adaptive application of voltage pulses to stabilize memory cell voltage levels Apr 4, 2021 Issued
Array ( [id] => 17917180 [patent_doc_number] => 20220319576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => APPARATUSES AND METHODS FOR SINGLE-ENDED GLOBAL AND LOCAL INPUT/OUTPUT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/217981 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217981
Apparatuses and methods for single-ended global and local input/output architecture Mar 29, 2021 Issued
Array ( [id] => 18031800 [patent_doc_number] => 11514995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Memory sub-system self-testing operations [patent_app_type] => utility [patent_app_number] => 17/211133 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10402 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211133
Memory sub-system self-testing operations Mar 23, 2021 Issued
Array ( [id] => 17485652 [patent_doc_number] => 20220093156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/205239 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205239
Memory system Mar 17, 2021 Issued
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