Patricia L Morris
Examiner (ID: 15529, Phone: (571)272-0688 , Office: P/1625 )
Most Active Art Unit | 1625 |
Art Unit(s) | 1203, 1201, 1612, 1209, 1625 |
Total Applications | 3798 |
Issued Applications | 2688 |
Pending Applications | 142 |
Abandoned Applications | 966 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16730911
[patent_doc_number] => 20210098059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => PRECISE WRITING OF MULTI-LEVEL WEIGHTS TO MEMORY DEVICES FOR COMPUTE-IN-MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/117795
[patent_app_country] => US
[patent_app_date] => 2020-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9237
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117795
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/117795 | Precise writing of multi-level weights to memory devices for compute-in-memory | Dec 9, 2020 | Issued |
Array
(
[id] => 16730913
[patent_doc_number] => 20210098061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => COMPARING INPUT DATA TO STORED DATA
[patent_app_type] => utility
[patent_app_number] => 17/118102
[patent_app_country] => US
[patent_app_date] => 2020-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118102
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/118102 | Comparing input data to stored data | Dec 9, 2020 | Issued |
Array
(
[id] => 17660483
[patent_doc_number] => 20220180948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => TEMPERATURE COMPENSATION FOR UNSELECTED SUB-BLOCK INHIBIT BIAS FOR MITIGATING ERASE DISTURB
[patent_app_type] => utility
[patent_app_number] => 17/113920
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13997
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113920
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/113920 | Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb | Dec 6, 2020 | Issued |
Array
(
[id] => 18292153
[patent_doc_number] => 11621026
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-04
[patent_title] => Write driver with magnetic field compensation
[patent_app_type] => utility
[patent_app_number] => 17/108411
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7632
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108411
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/108411 | Write driver with magnetic field compensation | Nov 30, 2020 | Issued |
Array
(
[id] => 17878380
[patent_doc_number] => 11450401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Method, system and computer program product for memory repair
[patent_app_type] => utility
[patent_app_number] => 17/108870
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 15176
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108870
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/108870 | Method, system and computer program product for memory repair | Nov 30, 2020 | Issued |
Array
(
[id] => 17682255
[patent_doc_number] => 11366507
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-21
[patent_title] => Storage device, semiconductor device, electronic component, and electronic device
[patent_app_type] => utility
[patent_app_number] => 17/104460
[patent_app_country] => US
[patent_app_date] => 2020-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 42
[patent_no_of_words] => 15240
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104460
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/104460 | Storage device, semiconductor device, electronic component, and electronic device | Nov 24, 2020 | Issued |
Array
(
[id] => 16715380
[patent_doc_number] => 20210082527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => MEMORIES HAVING MULTIPLE VOLTAGE GENERATION SYSTEMS CONNECTED TO A VOLTAGE REGULATOR
[patent_app_type] => utility
[patent_app_number] => 17/102602
[patent_app_country] => US
[patent_app_date] => 2020-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12908
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102602
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/102602 | Memories having multiple voltage generation systems connected to a voltage regulator | Nov 23, 2020 | Issued |
Array
(
[id] => 17302745
[patent_doc_number] => 20210398584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-23
[patent_title] => METHOD AND CIRCUIT FOR PROTECTING A DRAM MEMORY DEVICE FROM THE ROW HAMMER EFFECT
[patent_app_type] => utility
[patent_app_number] => 17/098044
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9512
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098044
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/098044 | Method and circuit for protecting a DRAM memory device from the row hammer effect | Nov 12, 2020 | Issued |
Array
(
[id] => 17757974
[patent_doc_number] => 11398272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 17/095000
[patent_app_country] => US
[patent_app_date] => 2020-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6964
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 356
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095000
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/095000 | Semiconductor memory device | Nov 10, 2020 | Issued |
Array
(
[id] => 16936109
[patent_doc_number] => 20210201998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-01
[patent_title] => NONVOLATILE SRAM
[patent_app_type] => utility
[patent_app_number] => 17/094307
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6491
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094307
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094307 | Nonvolatile SRAM | Nov 9, 2020 | Issued |
Array
(
[id] => 17606906
[patent_doc_number] => 11335398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-17
[patent_title] => Integrated circuit and memory
[patent_app_type] => utility
[patent_app_number] => 17/084910
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6218
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084910
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/084910 | Integrated circuit and memory | Oct 29, 2020 | Issued |
Array
(
[id] => 16981189
[patent_doc_number] => 20210225426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER
[patent_app_type] => utility
[patent_app_number] => 17/084345
[patent_app_country] => US
[patent_app_date] => 2020-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18959
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084345
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/084345 | Memory device transmitting and receiving data at high speed and low power | Oct 28, 2020 | Issued |
Array
(
[id] => 17469973
[patent_doc_number] => 11276455
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-03-15
[patent_title] => Systems and methods for memory device power off
[patent_app_type] => utility
[patent_app_number] => 17/082964
[patent_app_country] => US
[patent_app_date] => 2020-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 6249
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082964
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/082964 | Systems and methods for memory device power off | Oct 27, 2020 | Issued |
Array
(
[id] => 16765281
[patent_doc_number] => 20210110863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => SENSE AMPLIFIER WITH LOWER OFFSET AND INCREASED SPEED
[patent_app_type] => utility
[patent_app_number] => 17/078806
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25039
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078806
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/078806 | Sense amplifier with lower offset and increased speed | Oct 22, 2020 | Issued |
Array
(
[id] => 18039707
[patent_doc_number] => 20220383924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => TWO BIT MEMORY DEVICE AND METHOD FOR OPERATING THE TWO-BIT MEMORY DEVICE AND ELECTRONIC COMPONENT
[patent_app_type] => utility
[patent_app_number] => 17/771200
[patent_app_country] => US
[patent_app_date] => 2020-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11434
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771200
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/771200 | Two bit memory device and method for operating the two-bit memory device and electronic component | Oct 19, 2020 | Issued |
Array
(
[id] => 18219327
[patent_doc_number] => 11594273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => Row hammer detection and avoidance
[patent_app_type] => utility
[patent_app_number] => 17/070865
[patent_app_country] => US
[patent_app_date] => 2020-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5859
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070865
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/070865 | Row hammer detection and avoidance | Oct 13, 2020 | Issued |
Array
(
[id] => 16730917
[patent_doc_number] => 20210098065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => ARCHITECTURE FOR 3-D NAND MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/067577
[patent_app_country] => US
[patent_app_date] => 2020-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8898
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067577
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/067577 | Architecture for 3-D NAND memory | Oct 8, 2020 | Issued |
Array
(
[id] => 17573921
[patent_doc_number] => 11322195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-03
[patent_title] => Compute in memory system
[patent_app_type] => utility
[patent_app_number] => 17/034701
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7353
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034701
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/034701 | Compute in memory system | Sep 27, 2020 | Issued |
Array
(
[id] => 17508831
[patent_doc_number] => 20220101934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => MEMORY WITH CELLS HAVING MULTIPLE SELECT TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 17/032913
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7286
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032913
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/032913 | Memory with cells having multiple select transistors | Sep 24, 2020 | Issued |
Array
(
[id] => 16617342
[patent_doc_number] => 20210035995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS
[patent_app_type] => utility
[patent_app_number] => 17/027399
[patent_app_country] => US
[patent_app_date] => 2020-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15822
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027399
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/027399 | Memory device including pass transistors in memory tiers | Sep 20, 2020 | Issued |