Patrick C. Chen

Array ( [id] => 20259512 [patent_doc_number] => 12431879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Classical processor for quantum control [patent_app_type] => utility [patent_app_number] => 17/020135 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17803881 [patent_doc_number] => 11418198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Digital clock generation and variation control circuitry [patent_app_type] => utility [patent_app_number] => 17/005752 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10262 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16692951 [patent_doc_number] => 20210075430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/000962 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17811396 [patent_doc_number] => 20220263231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => DIGITAL PHASE SHIFTERS HAVING MULTI-THROW RADIO FREQUENCY SWITCHES AND RELATED METHODS OF OPERATION [patent_app_type] => utility [patent_app_number] => 17/626184 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17683913 [patent_doc_number] => 11368180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Switch circuits with parallel transistor stacks and methods of their operation [patent_app_type] => utility [patent_app_number] => 16/944612 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 12092 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16586855 [patent_doc_number] => 20210021257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Glitch Mitigation in Switched Reactance Phase Shifters [patent_app_type] => utility [patent_app_number] => 16/943626 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16529530 [patent_doc_number] => 20200403611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => ADVANCED GATE DRIVERS FOR SILICON CARBIDE BIPOLAR JUNCTION TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/927899 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16561095 [patent_doc_number] => 20210006244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => DRIVE CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/916839 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16379904 [patent_doc_number] => 20200328747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => DRIVER CIRCUITRY FOR FAST, EFFICIENT STATE TRANSITIONS [patent_app_type] => utility [patent_app_number] => 16/915464 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17816992 [patent_doc_number] => 11422599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => System and method for soft-start scheme to control inrush current for VCONN in USB-C interface [patent_app_type] => utility [patent_app_number] => 16/915857 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9057 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17456676 [patent_doc_number] => 11271547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Gate drive circuit, drive device, semiconductor device, and gate drive method [patent_app_type] => utility [patent_app_number] => 16/914858 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5891 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16509875 [patent_doc_number] => 20200389131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => AMPLIFICATION SYSTEMS AND METHODS WITH DISTORTION REDUCTIONS [patent_app_type] => utility [patent_app_number] => 16/914907 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17289458 [patent_doc_number] => 11206026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit [patent_app_type] => utility [patent_app_number] => 16/911888 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 23253 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16379895 [patent_doc_number] => 20200328738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => ADAPTIVE VOLTAGE SCALING SYSTEM FOR OUT OF CONTEXT FUNCTIONAL SAFETY SoC [patent_app_type] => utility [patent_app_number] => 16/912057 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16928858 [patent_doc_number] => 11050358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Power module with built-in drive circuit [patent_app_type] => utility [patent_app_number] => 16/909598 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5922 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17033471 [patent_doc_number] => 11095294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Phase-locked loop and method for calibrating voltage-controlled oscillator therein [patent_app_type] => utility [patent_app_number] => 16/909976 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6325 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 508 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18521173 [patent_doc_number] => 11711072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Serial bus redriver with trailing edge boost circuit [patent_app_type] => utility [patent_app_number] => 16/905264 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6687 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18593906 [patent_doc_number] => 11742821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Multiplexer, filter, and communication module [patent_app_type] => utility [patent_app_number] => 16/903207 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 6034 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16509910 [patent_doc_number] => 20200389166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => SWITCH WITH GATE OR BODY CONNECTED LINEARIZER [patent_app_type] => utility [patent_app_number] => 16/893188 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17796487 [patent_doc_number] => 20220255579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => COMMUNICATION DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/616539 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17616539 [rel_patent_id] =>[rel_patent_doc_number] =>)