
Patrick C. Chen
Examiner (ID: 16543, Phone: (571)270-7207 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2816, 2842 |
| Total Applications | 665 |
| Issued Applications | 516 |
| Pending Applications | 83 |
| Abandoned Applications | 98 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17284571
[patent_doc_number] => 11201619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-14
[patent_title] => Isolated high side drive circuit
[patent_app_type] => utility
[patent_app_number] => 16/483570
[patent_app_country] => US
[patent_app_date] => 2018-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 13929
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483570
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/483570 | Isolated high side drive circuit | Feb 6, 2018 | Issued |
Array
(
[id] => 12874786
[patent_doc_number] => 20180183437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => BOOTSTRAP DIODE CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 15/879231
[patent_app_country] => US
[patent_app_date] => 2018-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9864
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879231
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/879231 | Bootstrap diode circuits | Jan 23, 2018 | Issued |
Array
(
[id] => 12803023
[patent_doc_number] => 20180159511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => Positive Logic Digitally Tunable Capacitor
[patent_app_type] => utility
[patent_app_number] => 15/871643
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871643
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871643 | Positive logic digitally tunable capacitor | Jan 14, 2018 | Issued |
Array
(
[id] => 15047027
[patent_doc_number] => 20190334518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => UNIVERSAL SEMICONDUCTOR SWITCH
[patent_app_type] => utility
[patent_app_number] => 16/475144
[patent_app_country] => US
[patent_app_date] => 2017-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2004
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475144
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/475144 | UNIVERSAL SEMICONDUCTOR SWITCH | Dec 14, 2017 | Abandoned |
Array
(
[id] => 14239589
[patent_doc_number] => 20190131967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-02
[patent_title] => BUS DRIVER WITH RISE/FALL TIME CONTROL
[patent_app_type] => utility
[patent_app_number] => 15/834599
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834599
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834599 | Bus driver with rise/fall time control | Dec 6, 2017 | Issued |
Array
(
[id] => 12803116
[patent_doc_number] => 20180159542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS
[patent_app_type] => utility
[patent_app_number] => 15/833117
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833117
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833117 | Hitless re-arrangements in coupled digital phase-locked loops | Dec 5, 2017 | Issued |
Array
(
[id] => 14415243
[patent_doc_number] => 20190173465
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-06
[patent_title] => CONTROLLED CURRENT MANIPULATION FOR REGENERATIVE CHARGING OF GATE CAPACITANCE
[patent_app_type] => utility
[patent_app_number] => 15/833857
[patent_app_country] => US
[patent_app_date] => 2017-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6503
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833857
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/833857 | Controlled current manipulation for regenerative charging of gate capacitance | Dec 5, 2017 | Issued |
Array
(
[id] => 12803107
[patent_doc_number] => 20180159539
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => CLOCK DIVIDING FREQUENCY CIRCUIT, CONTROL CIRCUIT AND POWER MANAGEMENT INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 15/828610
[patent_app_country] => US
[patent_app_date] => 2017-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828610
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/828610 | Clock dividing frequency circuit, control circuit and power management integrated circuit | Nov 30, 2017 | Issued |
Array
(
[id] => 14604959
[patent_doc_number] => 10355679
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-16
[patent_title] => Display driving circuit, calibration module, and associated calibration method
[patent_app_type] => utility
[patent_app_number] => 15/828618
[patent_app_country] => US
[patent_app_date] => 2017-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5030
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828618
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/828618 | Display driving circuit, calibration module, and associated calibration method | Nov 30, 2017 | Issued |
Array
(
[id] => 12803029
[patent_doc_number] => 20180159513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => Retention Flip-Flop Circuits For Low Power Applications
[patent_app_type] => utility
[patent_app_number] => 15/826273
[patent_app_country] => US
[patent_app_date] => 2017-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826273
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/826273 | Retention flip-flop circuits for low power applications | Nov 28, 2017 | Issued |
Array
(
[id] => 17909202
[patent_doc_number] => 11463072
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-10-04
[patent_title] => Adaptive volterra compensator
[patent_app_type] => utility
[patent_app_number] => 15/807419
[patent_app_country] => US
[patent_app_date] => 2017-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10086
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807419
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/807419 | Adaptive volterra compensator | Nov 7, 2017 | Issued |
Array
(
[id] => 15155365
[patent_doc_number] => 20190356160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => CONTROL CIRCUIT COMPATIBLE WITH BATTERY POWER SUPPLY AND EXTERNAL POWER SUPPLY
[patent_app_type] => utility
[patent_app_number] => 16/476869
[patent_app_country] => US
[patent_app_date] => 2017-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5408
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476869
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/476869 | Control circuit compatible with battery power supply and external power supply | Oct 27, 2017 | Issued |
Array
(
[id] => 15824529
[patent_doc_number] => 10637468
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Galvanically-isolated signaling between modules with step-up transformer
[patent_app_type] => utility
[patent_app_number] => 15/790196
[patent_app_country] => US
[patent_app_date] => 2017-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 5990
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790196
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/790196 | Galvanically-isolated signaling between modules with step-up transformer | Oct 22, 2017 | Issued |
Array
(
[id] => 12651471
[patent_doc_number] => 20180108988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => SWITCH LINEARIZATION BY COMPENSATION OF A FIELD-EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 15/788789
[patent_app_country] => US
[patent_app_date] => 2017-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12217
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788789
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/788789 | Switch linearization by compensation of a field-effect transistor | Oct 18, 2017 | Issued |
Array
(
[id] => 14741309
[patent_doc_number] => 10390075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-20
[patent_title] => Semiconductor device, broadcasting system, and electronic device
[patent_app_type] => utility
[patent_app_number] => 15/729191
[patent_app_country] => US
[patent_app_date] => 2017-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 51
[patent_no_of_words] => 31836
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729191
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/729191 | Semiconductor device, broadcasting system, and electronic device | Oct 9, 2017 | Issued |
Array
(
[id] => 15374325
[patent_doc_number] => 10528885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-07
[patent_title] => Cross-resonance fan-out for efficiency and hardware reduction
[patent_app_type] => utility
[patent_app_number] => 15/720927
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5594
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720927
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/720927 | Cross-resonance fan-out for efficiency and hardware reduction | Sep 28, 2017 | Issued |
Array
(
[id] => 12597957
[patent_doc_number] => 20180091149
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => CIRCUIT AND METHOD FOR CHECKING THE INTEGRITY OF A CONTROL SIGNAL
[patent_app_type] => utility
[patent_app_number] => 15/718033
[patent_app_country] => US
[patent_app_date] => 2017-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4847
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718033
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/718033 | Circuit and method for checking the integrity of a control signal | Sep 27, 2017 | Issued |
Array
(
[id] => 15969265
[patent_doc_number] => 20200168384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => MAGNETIC CORE INDUCTORS
[patent_app_type] => utility
[patent_app_number] => 16/637006
[patent_app_country] => US
[patent_app_date] => 2017-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5377
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16637006
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/637006 | Magnetic core inductors | Sep 27, 2017 | Issued |
Array
(
[id] => 14111875
[patent_doc_number] => 20190097613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => METHODS AND APPARATUSES OF A TWO-PHASE FLIP-FLOP WITH SYMMETRICAL RISE AND FALL TIMES
[patent_app_type] => utility
[patent_app_number] => 15/717610
[patent_app_country] => US
[patent_app_date] => 2017-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717610
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/717610 | Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times | Sep 26, 2017 | Issued |
Array
(
[id] => 14254035
[patent_doc_number] => 10277230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-30
[patent_title] => Jitter reduction in clock and data recovery circuits
[patent_app_type] => utility
[patent_app_number] => 15/714719
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10529
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714719
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714719 | Jitter reduction in clock and data recovery circuits | Sep 24, 2017 | Issued |