Patrick C. Chen

Array ( [id] => 12357015 [patent_doc_number] => 09954523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Receiver for resonance-coupled signaling [patent_app_type] => utility [patent_app_number] => 15/296660 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5824 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15358915 [patent_doc_number] => 10528071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Electronic drive circuit [patent_app_type] => utility [patent_app_number] => 15/294041 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 7959 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11558231 [patent_doc_number] => 20170104478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'Operation of Double-Base Bipolar Transistors with Additional Timing Phases at Switching Transitions' [patent_app_type] => utility [patent_app_number] => 15/267085 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4355 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12336831 [patent_doc_number] => 09948281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Positive logic digitally tunable capacitor [patent_app_type] => utility [patent_app_number] => 15/256453 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15256453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12316482 [patent_doc_number] => 09941884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => AC coupled level shifting circuit [patent_app_type] => utility [patent_app_number] => 15/253769 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 13788 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13334299 [patent_doc_number] => 20180218687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => VOLTAGE CONVERTING CIRCUIT, VOLTAGE CONVERTING MTHOD, GATE DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/518362 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15518362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11740885 [patent_doc_number] => 09705485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'High-resolution current and method for generating a current' [patent_app_type] => utility [patent_app_number] => 15/208071 [patent_app_country] => US [patent_app_date] => 2016-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12357063 [patent_doc_number] => 09954539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Method and apparatus for clock phase generation [patent_app_type] => utility [patent_app_number] => 15/206634 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4279 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12459234 [patent_doc_number] => 09985619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Duty cycle corrector, semiconductor device including the same, and method of operating duty cycle corrector [patent_app_type] => utility [patent_app_number] => 15/206622 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12069 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12965989 [patent_doc_number] => 09874889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-23 [patent_title] => Voltage regulator [patent_app_type] => utility [patent_app_number] => 15/201046 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12109621 [patent_doc_number] => 09866111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-09 [patent_title] => 'Regulated charge pump circuit' [patent_app_type] => utility [patent_app_number] => 15/198802 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5615 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15890987 [patent_doc_number] => 10651857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Frequency based bias voltage scaling for phase locked loops [patent_app_type] => utility [patent_app_number] => 15/194999 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5442 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11946543 [patent_doc_number] => 20170250694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/193357 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13307677 [patent_doc_number] => 20180205375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => CIRCUIT ARRANGEMENT FOR A SECURE DIGITAL SWITCHED OUTPUT, TEST METHOD FOR AND OUTPUT MODULE FOR THE SAME [patent_app_type] => utility [patent_app_number] => 15/736391 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15736391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13725481 [patent_doc_number] => 20170373696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => Clock Alignment Scheme for Data Macros of DDR PHY [patent_app_type] => utility [patent_app_number] => 15/192594 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11725928 [patent_doc_number] => 09698799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Phase locked loop frequency calibration circuit and method' [patent_app_type] => utility [patent_app_number] => 15/191457 [patent_app_country] => US [patent_app_date] => 2016-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6640 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11552305 [patent_doc_number] => 09621172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'Phase-locked loop circuit and calibrating method thereof' [patent_app_type] => utility [patent_app_number] => 15/189445 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11658821 [patent_doc_number] => 09671817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-06 [patent_title] => 'Accumulator-based phase memory' [patent_app_type] => utility [patent_app_number] => 15/187895 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12316500 [patent_doc_number] => 09941890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Phase-locked loops with electrical overstress protection circuitry [patent_app_type] => utility [patent_app_number] => 15/187534 [patent_app_country] => US [patent_app_date] => 2016-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5252 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11723157 [patent_doc_number] => 09696005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Tunable lighting apparatus' [patent_app_type] => utility [patent_app_number] => 15/180411 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6132 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15180411 [rel_patent_id] =>[rel_patent_doc_number] =>)