Patrick C. Chen

Array ( [id] => 12109621 [patent_doc_number] => 09866111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-09 [patent_title] => 'Regulated charge pump circuit' [patent_app_type] => utility [patent_app_number] => 15/198802 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5615 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15890987 [patent_doc_number] => 10651857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Frequency based bias voltage scaling for phase locked loops [patent_app_type] => utility [patent_app_number] => 15/194999 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5442 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11946543 [patent_doc_number] => 20170250694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/193357 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13307677 [patent_doc_number] => 20180205375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => CIRCUIT ARRANGEMENT FOR A SECURE DIGITAL SWITCHED OUTPUT, TEST METHOD FOR AND OUTPUT MODULE FOR THE SAME [patent_app_type] => utility [patent_app_number] => 15/736391 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15736391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13725481 [patent_doc_number] => 20170373696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => Clock Alignment Scheme for Data Macros of DDR PHY [patent_app_type] => utility [patent_app_number] => 15/192594 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11725928 [patent_doc_number] => 09698799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Phase locked loop frequency calibration circuit and method' [patent_app_type] => utility [patent_app_number] => 15/191457 [patent_app_country] => US [patent_app_date] => 2016-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6640 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11552305 [patent_doc_number] => 09621172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'Phase-locked loop circuit and calibrating method thereof' [patent_app_type] => utility [patent_app_number] => 15/189445 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11658821 [patent_doc_number] => 09671817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-06 [patent_title] => 'Accumulator-based phase memory' [patent_app_type] => utility [patent_app_number] => 15/187895 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12316500 [patent_doc_number] => 09941890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Phase-locked loops with electrical overstress protection circuitry [patent_app_type] => utility [patent_app_number] => 15/187534 [patent_app_country] => US [patent_app_date] => 2016-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5252 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11723157 [patent_doc_number] => 09696005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Tunable lighting apparatus' [patent_app_type] => utility [patent_app_number] => 15/180411 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6132 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15180411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11476581 [patent_doc_number] => 20170063364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'CONTROL UNIT FOR A BRIDGE CIRCUIT, AND RELATED METHOD AND INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/163895 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6267 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11051463 [patent_doc_number] => 20160248423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'FEEDTHROUGH SIGNAL TRANSMISSION CIRCUIT AND APPARATUS AND METHOD UTILIZING PERMANENTLY ON BUFFER AND SWITCHABLE NORMAL BUFFER' [patent_app_type] => utility [patent_app_number] => 15/145779 [patent_app_country] => US [patent_app_date] => 2016-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8936 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12336846 [patent_doc_number] => 09948287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Level-shift circuits compatible with multiple supply voltage [patent_app_type] => utility [patent_app_number] => 15/145562 [patent_app_country] => US [patent_app_date] => 2016-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6381 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11044288 [patent_doc_number] => 20160241244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING A LOAD INDEPENDENT BUFFER' [patent_app_type] => utility [patent_app_number] => 15/135482 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6782 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12761518 [patent_doc_number] => 20180145674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SWITCHING POWER DEVICE [patent_app_type] => utility [patent_app_number] => 15/574502 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11125986 [patent_doc_number] => 20160322961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'INTEGRATED POWER SUPPLY FOR FIBER OPTIC COMMUNICATION DEVICES AND SUBSYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/090614 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8136 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12355227 [patent_doc_number] => 09953921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Semiconductor device and semiconductor package [patent_app_type] => utility [patent_app_number] => 15/090212 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3996 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11021753 [patent_doc_number] => 20160218708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'GATE DRIVE APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/089430 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5815 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11984493 [patent_doc_number] => 20170288648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'Pulse-Width Modulation Voltage Identification Interface' [patent_app_type] => utility [patent_app_number] => 15/087892 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11984507 [patent_doc_number] => 20170288662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'System and Method for a High-Side Power Switch' [patent_app_type] => utility [patent_app_number] => 15/087342 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5962 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087342 [rel_patent_id] =>[rel_patent_doc_number] =>)