Search

Patrick C. Chen

Examiner (ID: 16543, Phone: (571)270-7207 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2816, 2842
Total Applications
665
Issued Applications
516
Pending Applications
83
Abandoned Applications
98

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10132758 [patent_doc_number] => 09166607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Capacitor leakage compensation for PLL loop filter capacitor' [patent_app_type] => utility [patent_app_number] => 13/409348 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6825 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13409348 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/409348
Capacitor leakage compensation for PLL loop filter capacitor Feb 29, 2012 Issued
Array ( [id] => 8826472 [patent_doc_number] => 20130127517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'DEBOUNCE APPARATUS AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/337816 [patent_app_country] => US [patent_app_date] => 2011-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3939 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13337816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/337816
Debounce apparatus and method thereof Dec 26, 2011 Issued
Array ( [id] => 10917158 [patent_doc_number] => 20140320178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'INTELLIGENT GATE DRIVER FOR IGBT' [patent_app_type] => utility [patent_app_number] => 14/358103 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14358103 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/358103
Intelligent gate driver for IGBT Nov 21, 2011 Issued
Array ( [id] => 11180855 [patent_doc_number] => 09412853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Protective device for a voltage-controlled semiconductor switch' [patent_app_type] => utility [patent_app_number] => 14/356662 [patent_app_country] => US [patent_app_date] => 2011-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2949 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356662 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356662
Protective device for a voltage-controlled semiconductor switch Nov 6, 2011 Issued
Array ( [id] => 7782451 [patent_doc_number] => 20120044007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'COMMUNICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/284614 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2784 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20120044007.pdf [firstpage_image] =>[orig_patent_app_number] => 13284614 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/284614
COMMUNICATION DEVICE Oct 27, 2011 Abandoned
Array ( [id] => 8750155 [patent_doc_number] => 08415990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Gate driving circuit' [patent_app_type] => utility [patent_app_number] => 13/281451 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6101 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13281451 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/281451
Gate driving circuit Oct 25, 2011 Issued
Array ( [id] => 9923860 [patent_doc_number] => 08981832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Amplification systems and methods with distortion reductions' [patent_app_type] => utility [patent_app_number] => 13/273061 [patent_app_country] => US [patent_app_date] => 2011-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7493 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13273061 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/273061
Amplification systems and methods with distortion reductions Oct 12, 2011 Issued
Array ( [id] => 8753960 [patent_doc_number] => 20130088264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'System, Drivers for Switches and Methods for Synchronizing Measurements of Analog-to-Digital Converters' [patent_app_type] => utility [patent_app_number] => 13/269889 [patent_app_country] => US [patent_app_date] => 2011-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4151 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/269889
System, drivers for switches and methods for synchronizing measurements of analog-to-digital converters Oct 9, 2011 Issued
Array ( [id] => 8135009 [patent_doc_number] => 20120092055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR KICKBACK NOISE REDUCTION OF SWITCHED CAPACITIVE LOADS AND METHOD OF OPERATING THE ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/267661 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20120092055.pdf [firstpage_image] =>[orig_patent_app_number] => 13267661 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267661
Electronic device and method for kickback noise reduction of switched capacitive loads and method of operating the electronic device Oct 5, 2011 Issued
Array ( [id] => 8743023 [patent_doc_number] => 20130082740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'CONFIGURABLE ANALOG FRONT END' [patent_app_type] => utility [patent_app_number] => 13/249349 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/249349
Configurable analog front end Sep 29, 2011 Issued
Array ( [id] => 9051888 [patent_doc_number] => 20130249603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING A LOAD INDEPENDENT BUFFER' [patent_app_type] => utility [patent_app_number] => 13/991881 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6731 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991881 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991881
Method and apparatus for improving a load independent buffer Sep 28, 2011 Issued
Array ( [id] => 13598659 [patent_doc_number] => 20180350878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Method and Apparatus for a Transmission Gate for Multi-GB/s Application [patent_app_type] => utility [patent_app_number] => 13/244429 [patent_app_country] => US [patent_app_date] => 2011-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/244429
Method and Apparatus for a Transmission Gate for Multi-GB/s Application Sep 23, 2011 Abandoned
Array ( [id] => 8730855 [patent_doc_number] => 20130076424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS' [patent_app_type] => utility [patent_app_number] => 13/242469 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13242469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/242469
SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS Sep 22, 2011 Abandoned
Array ( [id] => 8681568 [patent_doc_number] => 20130049852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'MOFSET MISMATCH CHARACTERIZATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/222323 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13222323 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222323
MOFSET mismatch characterization circuit Aug 30, 2011 Issued
Array ( [id] => 8681504 [patent_doc_number] => 20130049788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'MOFSET MISMATCH CHARACTERIZATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/222335 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13222335 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222335
MOFSET mismatch characterization circuit Aug 30, 2011 Issued
Array ( [id] => 8681559 [patent_doc_number] => 20130049843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER' [patent_app_type] => utility [patent_app_number] => 13/219219 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7132 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219219 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219219
REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER Aug 25, 2011 Abandoned
Array ( [id] => 8705905 [patent_doc_number] => 20130063194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'Circuit for the Clocking of an FPGA' [patent_app_type] => utility [patent_app_number] => 13/696945 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2011 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13696945 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/696945
Circuit for the clocking of an FPGA Apr 13, 2011 Issued
Array ( [id] => 8851475 [patent_doc_number] => 20130141150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/637427 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1356 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13637427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/637427
METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL Mar 16, 2011 Abandoned
Array ( [id] => 10112761 [patent_doc_number] => 09148184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Power detection circuit and power detection method' [patent_app_type] => utility [patent_app_number] => 13/579871 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 7093 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13579871 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/579871
Power detection circuit and power detection method Dec 14, 2010 Issued
Array ( [id] => 6076147 [patent_doc_number] => 20110140713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'FUSE DRIVER CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/965611 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3480 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140713.pdf [firstpage_image] =>[orig_patent_app_number] => 12965611 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965611
Fuse driver circuits Dec 9, 2010 Issued
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