Search

Patrick C. Chen

Examiner (ID: 1056)

Most Active Art Unit
2842
Art Unit(s)
2836, 2816, 2842
Total Applications
707
Issued Applications
540
Pending Applications
80
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9051888 [patent_doc_number] => 20130249603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING A LOAD INDEPENDENT BUFFER' [patent_app_type] => utility [patent_app_number] => 13/991881 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6731 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991881 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991881
Method and apparatus for improving a load independent buffer Sep 28, 2011 Issued
Array ( [id] => 13598659 [patent_doc_number] => 20180350878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Method and Apparatus for a Transmission Gate for Multi-GB/s Application [patent_app_type] => utility [patent_app_number] => 13/244429 [patent_app_country] => US [patent_app_date] => 2011-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/244429
Method and Apparatus for a Transmission Gate for Multi-GB/s Application Sep 23, 2011 Abandoned
Array ( [id] => 8730855 [patent_doc_number] => 20130076424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS' [patent_app_type] => utility [patent_app_number] => 13/242469 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13242469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/242469
SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS Sep 22, 2011 Abandoned
Array ( [id] => 8681568 [patent_doc_number] => 20130049852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'MOFSET MISMATCH CHARACTERIZATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/222323 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13222323 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222323
MOFSET mismatch characterization circuit Aug 30, 2011 Issued
Array ( [id] => 8681504 [patent_doc_number] => 20130049788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'MOFSET MISMATCH CHARACTERIZATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/222335 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13222335 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222335
MOFSET mismatch characterization circuit Aug 30, 2011 Issued
Array ( [id] => 8681559 [patent_doc_number] => 20130049843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER' [patent_app_type] => utility [patent_app_number] => 13/219219 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7132 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219219 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219219
REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER Aug 25, 2011 Abandoned
Array ( [id] => 8705905 [patent_doc_number] => 20130063194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'Circuit for the Clocking of an FPGA' [patent_app_type] => utility [patent_app_number] => 13/696945 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2011 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13696945 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/696945
Circuit for the clocking of an FPGA Apr 13, 2011 Issued
Array ( [id] => 8851475 [patent_doc_number] => 20130141150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/637427 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1356 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13637427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/637427
METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL Mar 16, 2011 Abandoned
Array ( [id] => 10112761 [patent_doc_number] => 09148184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Power detection circuit and power detection method' [patent_app_type] => utility [patent_app_number] => 13/579871 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 7093 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13579871 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/579871
Power detection circuit and power detection method Dec 14, 2010 Issued
Array ( [id] => 6076147 [patent_doc_number] => 20110140713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'FUSE DRIVER CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/965611 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3480 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140713.pdf [firstpage_image] =>[orig_patent_app_number] => 12965611 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965611
Fuse driver circuits Dec 9, 2010 Issued
Array ( [id] => 8859341 [patent_doc_number] => 08461882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Driver supporting multiple signaling modes' [patent_app_type] => utility [patent_app_number] => 13/255844 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2142 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13255844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/255844
Driver supporting multiple signaling modes May 6, 2010 Issued
Array ( [id] => 8583513 [patent_doc_number] => 20130002334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD FOR CONFIGURING A SIGNAL PATH FOR A TIMING SENSITIVE SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/634992 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6113 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13634992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/634992
INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD FOR CONFIGURING A SIGNAL PATH FOR A TIMING SENSITIVE SIGNAL Mar 21, 2010 Abandoned
Array ( [id] => 11195078 [patent_doc_number] => 09425902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'System including driver circuit for electrical signaling and optical signaling' [patent_app_type] => utility [patent_app_number] => 13/386632 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6570 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13386632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/386632
System including driver circuit for electrical signaling and optical signaling Jan 10, 2010 Issued
Array ( [id] => 6037060 [patent_doc_number] => 20110090109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'Charge pump' [patent_app_type] => utility [patent_app_number] => 12/308288 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4078 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20110090109.pdf [firstpage_image] =>[orig_patent_app_number] => 12308288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/308288
Charge pump Oct 1, 2007 Abandoned
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