Patrick Dennis Niland

Array ( [id] => 9980649 [patent_doc_number] => 09026980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Methods and systems for performing signal activity extraction' [patent_app_type] => utility [patent_app_number] => 14/199922 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7726 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9714569 [patent_doc_number] => 08839172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-16 [patent_title] => 'Specification of latency in programmable device configuration' [patent_app_type] => utility [patent_app_number] => 14/197770 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4345 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14197770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10204473 [patent_doc_number] => 20150089461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'METHODS FOR GENERATING SCHEMATIC DIAGRAMS AND APPARATUSES USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/084437 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3115 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9358739 [patent_doc_number] => 08677295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design' [patent_app_type] => utility [patent_app_number] => 14/083109 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4522 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10228503 [patent_doc_number] => 20150113496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'THERMALLY AWARE PIN ASSIGNMENT AND DEVICE PLACEMENT' [patent_app_type] => utility [patent_app_number] => 14/056007 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9940919 [patent_doc_number] => 08990750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Numerical area recovery' [patent_app_type] => utility [patent_app_number] => 13/954927 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10052072 [patent_doc_number] => 09091946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Method and system for forming non-manhattan patterns using variable shaped beam lithography' [patent_app_type] => utility [patent_app_number] => 13/948725 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 8052 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9150681 [patent_doc_number] => 20130305204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS' [patent_app_type] => utility [patent_app_number] => 13/946941 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5466 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10873387 [patent_doc_number] => 08898608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method for displaying timing information of an integrated circuit floorplan' [patent_app_type] => utility [patent_app_number] => 13/942177 [patent_app_country] => US [patent_app_date] => 2013-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9781478 [patent_doc_number] => 08856702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Method and apparatus for performing multiple stage physical synthesis' [patent_app_type] => utility [patent_app_number] => 13/935633 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7325 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10879538 [patent_doc_number] => 08904336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Determination of meta-stable latch bias voltages' [patent_app_type] => utility [patent_app_number] => 13/931917 [patent_app_country] => US [patent_app_date] => 2013-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9045 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9123994 [patent_doc_number] => 20130290915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'COMPUTATIONAL EFFICIENCY IN PHOTOLITHOGRAPHIC PROCESS SIMULATION' [patent_app_type] => utility [patent_app_number] => 13/930912 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13252 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9821074 [patent_doc_number] => 08930877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method and system of change evaluation of an electronic design for verification confirmation' [patent_app_type] => utility [patent_app_number] => 13/929007 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7726 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13929007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10901658 [patent_doc_number] => 08924905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Constructing equivalent waveform models for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 13/924516 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 10062 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9652382 [patent_doc_number] => 08806418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Scaled sigma sampling' [patent_app_type] => utility [patent_app_number] => 13/921897 [patent_app_country] => US [patent_app_date] => 2013-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9520725 [patent_doc_number] => 20140157217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEQUENTIAL NON-DETERMINISTIC DETECTION IN HARDWARE DESIGN' [patent_app_type] => utility [patent_app_number] => 13/909747 [patent_app_country] => US [patent_app_date] => 2013-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6584 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9555845 [patent_doc_number] => 08762918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Banded computation architectures' [patent_app_type] => utility [patent_app_number] => 13/908937 [patent_app_country] => US [patent_app_date] => 2013-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8680 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10890744 [patent_doc_number] => 08914758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-16 [patent_title] => 'Equivalence checking using structural analysis on data flow graphs' [patent_app_type] => utility [patent_app_number] => 13/903967 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7940 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10890748 [patent_doc_number] => 08914761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Metastability effects simulation for a circuit description' [patent_app_type] => utility [patent_app_number] => 13/888036 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 20854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9974377 [patent_doc_number] => 09021414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-28 [patent_title] => 'Automation for monolithic 3D devices' [patent_app_type] => utility [patent_app_number] => 13/862537 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862537 [rel_patent_id] =>[rel_patent_doc_number] =>)