Search

Patrick Dennis Niland

Examiner (ID: 1494, Phone: (571)272-1121 , Office: P/1762 )

Most Active Art Unit
1762
Art Unit(s)
1796, 1509, 1714, 1511, 1762
Total Applications
2822
Issued Applications
1804
Pending Applications
181
Abandoned Applications
837

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8011133 [patent_doc_number] => 08086985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Automatic alignment of macro cells' [patent_app_type] => utility [patent_app_number] => 12/235817 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6465 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086985.pdf [firstpage_image] =>[orig_patent_app_number] => 12235817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/235817
Automatic alignment of macro cells Sep 22, 2008 Issued
Array ( [id] => 7813542 [patent_doc_number] => 08136080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Graphic rendering of circuit positions' [patent_app_type] => utility [patent_app_number] => 12/234817 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6968 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136080.pdf [firstpage_image] =>[orig_patent_app_number] => 12234817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234817
Graphic rendering of circuit positions Sep 21, 2008 Issued
Array ( [id] => 8149407 [patent_doc_number] => 08166424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Method for constructing OPC model' [patent_app_type] => utility [patent_app_number] => 12/211657 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166424.pdf [firstpage_image] =>[orig_patent_app_number] => 12211657 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211657
Method for constructing OPC model Sep 15, 2008 Issued
Array ( [id] => 4621774 [patent_doc_number] => 08001505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Method and apparatus for merging EDA coverage logs of coverage data' [patent_app_type] => utility [patent_app_number] => 12/210887 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8892 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001505.pdf [firstpage_image] =>[orig_patent_app_number] => 12210887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/210887
Method and apparatus for merging EDA coverage logs of coverage data Sep 14, 2008 Issued
Array ( [id] => 6621614 [patent_doc_number] => 20100064269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'METHOD AND SYSTEM FOR DESIGN RULE CHECKING ENHANCED WITH PATTERN MATCHING' [patent_app_type] => utility [patent_app_number] => 12/208167 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4849 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064269.pdf [firstpage_image] =>[orig_patent_app_number] => 12208167 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/208167
Method and system for design rule checking enhanced with pattern matching Sep 9, 2008 Issued
Array ( [id] => 5326075 [patent_doc_number] => 20090064065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Method of verifying circuit and computer-readable storage medium for storing computer program' [patent_app_type] => utility [patent_app_number] => 12/230387 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8518 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20090064065.pdf [firstpage_image] =>[orig_patent_app_number] => 12230387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/230387
Method of verifying circuit and computer-readable storage medium for storing computer program Aug 27, 2008 Issued
Array ( [id] => 4455165 [patent_doc_number] => 07966596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Place-and-route layout method with same footprint cells' [patent_app_type] => utility [patent_app_number] => 12/199617 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1706 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966596.pdf [firstpage_image] =>[orig_patent_app_number] => 12199617 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199617
Place-and-route layout method with same footprint cells Aug 26, 2008 Issued
Array ( [id] => 5438031 [patent_doc_number] => 20090172618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'TECHNIQUE FOR CREATING ANALYSIS MODEL AND TECHNIQUE FOR CREATING CIRCUIT BOARD MODEL' [patent_app_type] => utility [patent_app_number] => 12/193867 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 18581 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172618.pdf [firstpage_image] =>[orig_patent_app_number] => 12193867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193867
Technique for creating analysis model and technique for creating circuit board model Aug 18, 2008 Issued
Array ( [id] => 5312137 [patent_doc_number] => 20090019418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium' [patent_app_type] => utility [patent_app_number] => 12/222479 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6163 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019418.pdf [firstpage_image] =>[orig_patent_app_number] => 12222479 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222479
Mask pattern preparation method, semiconductor device manufacturing method and recording medium Aug 10, 2008 Issued
Array ( [id] => 4793900 [patent_doc_number] => 20080294874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'ALLOCATION OF COMBINED OR SEPARATE DATA AND CONTROL PLANES' [patent_app_type] => utility [patent_app_number] => 12/186622 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4025 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294874.pdf [firstpage_image] =>[orig_patent_app_number] => 12186622 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186622
Allocation of combined or separate data and control planes Aug 5, 2008 Issued
Array ( [id] => 118461 [patent_doc_number] => 07716614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Hierarchical feature extraction for electrical interaction calculations' [patent_app_type] => utility [patent_app_number] => 12/177018 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5564 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716614.pdf [firstpage_image] =>[orig_patent_app_number] => 12177018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177018
Hierarchical feature extraction for electrical interaction calculations Jul 20, 2008 Issued
Array ( [id] => 7548039 [patent_doc_number] => 08056020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Method of designing semiconductor integrated circuit and mask data generation program' [patent_app_type] => utility [patent_app_number] => 12/219057 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8630 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056020.pdf [firstpage_image] =>[orig_patent_app_number] => 12219057 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219057
Method of designing semiconductor integrated circuit and mask data generation program Jul 14, 2008 Issued
Array ( [id] => 5467787 [patent_doc_number] => 20090327987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Timing operations in an IC with configurable circuits' [patent_app_type] => utility [patent_app_number] => 12/215697 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 20119 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327987.pdf [firstpage_image] =>[orig_patent_app_number] => 12215697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215697
Timing operations in an IC with configurable circuits Jun 25, 2008 Issued
Array ( [id] => 7548052 [patent_doc_number] => 08056033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Apparatus and method for integrated circuit design with improved delay variation calculation based on power supply variations' [patent_app_type] => utility [patent_app_number] => 12/213557 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11544 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056033.pdf [firstpage_image] =>[orig_patent_app_number] => 12213557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213557
Apparatus and method for integrated circuit design with improved delay variation calculation based on power supply variations Jun 19, 2008 Issued
Array ( [id] => 4826351 [patent_doc_number] => 20080229265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees' [patent_app_type] => utility [patent_app_number] => 12/129748 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9988 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229265.pdf [firstpage_image] =>[orig_patent_app_number] => 12129748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129748
Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees May 29, 2008 Abandoned
Array ( [id] => 4508932 [patent_doc_number] => 07958469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Design structure for a phase locked loop with stabilized dynamic response' [patent_app_type] => utility [patent_app_number] => 12/128678 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10984 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958469.pdf [firstpage_image] =>[orig_patent_app_number] => 12128678 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128678
Design structure for a phase locked loop with stabilized dynamic response May 28, 2008 Issued
Array ( [id] => 5491959 [patent_doc_number] => 20090293030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Concurrently Modeling Delays Between Points in Static Timing Analysis Operation' [patent_app_type] => utility [patent_app_number] => 12/126037 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20090293030.pdf [firstpage_image] =>[orig_patent_app_number] => 12126037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126037
Concurrently modeling delays between points in static timing analysis operation May 22, 2008 Issued
Array ( [id] => 4889154 [patent_doc_number] => 20080263486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'VARIOUS METHODS AND APPARATUSES FOR CYCLE ACCURATE C-MODELS OF COMPONENTS' [patent_app_type] => utility [patent_app_number] => 12/122988 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8872 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263486.pdf [firstpage_image] =>[orig_patent_app_number] => 12122988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122988
Various methods and apparatuses for cycle accurate C-models of components May 18, 2008 Issued
Array ( [id] => 108176 [patent_doc_number] => 07725871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'SAT-based technology mapping framework' [patent_app_type] => utility [patent_app_number] => 12/123396 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8263 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725871.pdf [firstpage_image] =>[orig_patent_app_number] => 12123396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123396
SAT-based technology mapping framework May 18, 2008 Issued
Array ( [id] => 4632015 [patent_doc_number] => 08010925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Method and system for placement of electric circuit components in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/121397 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4873 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010925.pdf [firstpage_image] =>[orig_patent_app_number] => 12121397 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121397
Method and system for placement of electric circuit components in integrated circuit design May 14, 2008 Issued
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