Patrick Dennis Niland

Array ( [id] => 8794451 [patent_doc_number] => 20130111420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'MASK DATA PRODUCING METHOD AND MASK DATA PRODUCING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/725612 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 19815 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9564061 [patent_doc_number] => 20140181774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'NON-INTEGER HEIGHT STANDARD CELL LIBRARY' [patent_app_type] => utility [patent_app_number] => 13/725870 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6089 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9520721 [patent_doc_number] => 20140157213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'METHOD OF GENERATING A SET OF DEFECT CANDIDATES FOR WAFER' [patent_app_type] => utility [patent_app_number] => 13/692396 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4089 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9707536 [patent_doc_number] => 08832632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-09 [patent_title] => 'Compact routing' [patent_app_type] => utility [patent_app_number] => 13/660887 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8669058 [patent_doc_number] => 20130043596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/655935 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8992068 [patent_doc_number] => 20130219349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'METHOD FOR PROCESS PROXIMITY CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/626370 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13626370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9102877 [patent_doc_number] => 08566771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Automation of interconnect and routing customization' [patent_app_type] => utility [patent_app_number] => 13/623230 [patent_app_country] => US [patent_app_date] => 2012-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13623230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8613906 [patent_doc_number] => 20130019218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'HIGH-SPEED SRAM' [patent_app_type] => utility [patent_app_number] => 13/622419 [patent_app_country] => US [patent_app_date] => 2012-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9372527 [patent_doc_number] => 20140082400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'ENHANCED CLOCK GATING IN RETIMED MODULES' [patent_app_type] => utility [patent_app_number] => 13/620040 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13620040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10000971 [patent_doc_number] => 09045048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Charging control apparatus, charging system, and charging control method' [patent_app_type] => utility [patent_app_number] => 13/618541 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7168 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9365524 [patent_doc_number] => 20140075397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'PITCH-AWARE MULTI-PATTERNING LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/612790 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9156919 [patent_doc_number] => 08589833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Method for the definition of a library of application-domain-specific logic cells' [patent_app_type] => utility [patent_app_number] => 13/609789 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5852 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 740 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9365525 [patent_doc_number] => 20140075398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'Method and Apparatus for Process Window Modeling' [patent_app_type] => utility [patent_app_number] => 13/610390 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6722 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9143581 [patent_doc_number] => 08584063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-12 [patent_title] => 'Assertion-based design partitioning' [patent_app_type] => utility [patent_app_number] => 13/606980 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13606980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8568857 [patent_doc_number] => 20120331428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 13/606055 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11672 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13606055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187244 [patent_doc_number] => 08627245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Density balancing in multiple patterning lithography using integrated circuit layout fill' [patent_app_type] => utility [patent_app_number] => 13/596140 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6008 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13596140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8752265 [patent_doc_number] => 08418109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Semiconductor integrated circuit with multi-cut via and automated layout method for the same' [patent_app_type] => utility [patent_app_number] => 13/586070 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5061 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9297215 [patent_doc_number] => 20140040849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'QUANTUM GATE OPTIMIZATIONS' [patent_app_type] => utility [patent_app_number] => 13/567330 [patent_app_country] => US [patent_app_date] => 2012-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3850 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13567330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9276129 [patent_doc_number] => 08640077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Capturing mutual coupling effects between an integrated circuit chip and chip package' [patent_app_type] => utility [patent_app_number] => 13/561760 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187247 [patent_doc_number] => 08627248 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Verification for functional independence of logic designs that use redundant representation' [patent_app_type] => utility [patent_app_number] => 13/561000 [patent_app_country] => US [patent_app_date] => 2012-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8603 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561000 [rel_patent_id] =>[rel_patent_doc_number] =>)