![](/images/general/no_picture/200_user.png)
Patrick Dennis Niland
Examiner (ID: 1494, Phone: (571)272-1121 , Office: P/1762 )
Most Active Art Unit | 1762 |
Art Unit(s) | 1796, 1509, 1714, 1511, 1762 |
Total Applications | 2822 |
Issued Applications | 1804 |
Pending Applications | 181 |
Abandoned Applications | 837 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
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[id] => 9824175
[patent_doc_number] => 08933662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'Charging apparatus for lead storage battery'
[patent_app_type] => utility
[patent_app_number] => 13/558871
[patent_app_country] => US
[patent_app_date] => 2012-07-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/558871 | Charging apparatus for lead storage battery | Jul 25, 2012 | Issued |
Array
(
[id] => 9879122
[patent_doc_number] => 08966419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'System and method for testing stacked dies'
[patent_app_type] => utility
[patent_app_number] => 13/546037
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/546037 | System and method for testing stacked dies | Jul 10, 2012 | Issued |
Array
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[patent_doc_number] => 08595680
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[patent_kind] => B1
[patent_issue_date] => 2013-11-26
[patent_title] => 'Constrained random error injection for functional verification'
[patent_app_type] => utility
[patent_app_number] => 13/524390
[patent_app_country] => US
[patent_app_date] => 2012-06-15
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Array
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[patent_doc_number] => 20120317525
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[patent_kind] => A1
[patent_issue_date] => 2012-12-13
[patent_title] => 'IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH DIGESTS'
[patent_app_type] => utility
[patent_app_number] => 13/492630
[patent_app_country] => US
[patent_app_date] => 2012-06-08
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/492630 | Identifying hierarchical chip design intellectual property through digests | Jun 7, 2012 | Issued |
Array
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[id] => 9257962
[patent_doc_number] => 08621405
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[patent_issue_date] => 2013-12-31
[patent_title] => 'Incremental elmore delay calculation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/485600 | Incremental elmore delay calculation | May 30, 2012 | Issued |
Array
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[patent_doc_number] => 20120306440
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[patent_issue_date] => 2012-12-06
[patent_title] => 'HANDHELD ELECTRONIC DEVICE WITH POSITIONING FUNCTION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/478195 | Handheld electronic device with positioning function | May 22, 2012 | Issued |
Array
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[patent_doc_number] => 08627241
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[patent_title] => 'Pattern correction with location effect'
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[patent_app_number] => 13/447857
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/447857 | Pattern correction with location effect | Apr 15, 2012 | Issued |
Array
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[patent_doc_number] => 08645902
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[patent_issue_date] => 2014-02-04
[patent_title] => 'Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness'
[patent_app_type] => utility
[patent_app_number] => 13/445847
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/445847 | Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness | Apr 11, 2012 | Issued |
Array
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[id] => 8315107
[patent_doc_number] => 20120192131
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[patent_issue_date] => 2012-07-26
[patent_title] => 'Partial Hardening of a Software Program from a Software Implementation to a Hardware Implementation'
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[patent_app_number] => 13/431029
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Array
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[id] => 8299490
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[patent_issue_date] => 2012-07-19
[patent_title] => 'TIMING OPERATIONS IN AN IC WITH CONFIGURABLE CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 13/430674
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/430674 | Timing operations in an IC with configurable circuits | Mar 25, 2012 | Issued |
Array
(
[id] => 8479362
[patent_doc_number] => 20120278770
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[patent_issue_date] => 2012-11-01
[patent_title] => 'METHOD AND SYSTEM FOR FORMING NON-MANHATTAN PATTERNS USING VARIABLE SHAPED BEAM LITHOGRAPHY'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/429357 | METHOD AND SYSTEM FOR FORMING NON-MANHATTAN PATTERNS USING VARIABLE SHAPED BEAM LITHOGRAPHY | Mar 23, 2012 | Abandoned |
Array
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[id] => 9044350
[patent_doc_number] => 20130246988
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[patent_issue_date] => 2013-09-19
[patent_title] => 'SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR HIERARCHICAL FORMAL HARDWARE VERIFICATION OF FLOATING-POINT DIVISION AND/OR SQUARE ROOT ALGORITHMIC DESIGNS USING AUTOMATIC SEQUENTIAL EQUIVALENCE CHECKING'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/423097 | System, method, and computer program product for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking | Mar 15, 2012 | Issued |
Array
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[id] => 9012595
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[patent_title] => 'Dissection splitting with optical proximity correction to reduce corner rounding'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/350295 | Graphic rendering of circuit positions | Jan 12, 2012 | Issued |