Search

Patrick Dennis Niland

Examiner (ID: 1494, Phone: (571)272-1121 , Office: P/1762 )

Most Active Art Unit
1762
Art Unit(s)
1796, 1509, 1714, 1511, 1762
Total Applications
2822
Issued Applications
1804
Pending Applications
181
Abandoned Applications
837

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9824175 [patent_doc_number] => 08933662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Charging apparatus for lead storage battery' [patent_app_type] => utility [patent_app_number] => 13/558871 [patent_app_country] => US [patent_app_date] => 2012-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7326 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558871 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558871
Charging apparatus for lead storage battery Jul 25, 2012 Issued
Array ( [id] => 9879122 [patent_doc_number] => 08966419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'System and method for testing stacked dies' [patent_app_type] => utility [patent_app_number] => 13/546037 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3716 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546037 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546037
System and method for testing stacked dies Jul 10, 2012 Issued
Array ( [id] => 9169986 [patent_doc_number] => 08595680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-26 [patent_title] => 'Constrained random error injection for functional verification' [patent_app_type] => utility [patent_app_number] => 13/524390 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10382 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13524390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/524390
Constrained random error injection for functional verification Jun 14, 2012 Issued
Array ( [id] => 8518117 [patent_doc_number] => 20120317525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH DIGESTS' [patent_app_type] => utility [patent_app_number] => 13/492630 [patent_app_country] => US [patent_app_date] => 2012-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8144 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13492630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/492630
Identifying hierarchical chip design intellectual property through digests Jun 7, 2012 Issued
Array ( [id] => 9257962 [patent_doc_number] => 08621405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Incremental elmore delay calculation' [patent_app_type] => utility [patent_app_number] => 13/485600 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13485600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/485600
Incremental elmore delay calculation May 30, 2012 Issued
Array ( [id] => 8507032 [patent_doc_number] => 20120306440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'HANDHELD ELECTRONIC DEVICE WITH POSITIONING FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/478195 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3747 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/478195
Handheld electronic device with positioning function May 22, 2012 Issued
Array ( [id] => 9187240 [patent_doc_number] => 08627241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Pattern correction with location effect' [patent_app_type] => utility [patent_app_number] => 13/447857 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5969 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447857 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/447857
Pattern correction with location effect Apr 15, 2012 Issued
Array ( [id] => 9289544 [patent_doc_number] => 08645902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-04 [patent_title] => 'Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness' [patent_app_type] => utility [patent_app_number] => 13/445847 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13232 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445847 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445847
Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness Apr 11, 2012 Issued
Array ( [id] => 8315107 [patent_doc_number] => 20120192131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Partial Hardening of a Software Program from a Software Implementation to a Hardware Implementation' [patent_app_type] => utility [patent_app_number] => 13/431029 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431029 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431029
Partial hardening of a software program from a software implementation to a hardware implementation Mar 26, 2012 Issued
Array ( [id] => 8299490 [patent_doc_number] => 20120182046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'TIMING OPERATIONS IN AN IC WITH CONFIGURABLE CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/430674 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 20119 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430674 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430674
Timing operations in an IC with configurable circuits Mar 25, 2012 Issued
Array ( [id] => 8479362 [patent_doc_number] => 20120278770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'METHOD AND SYSTEM FOR FORMING NON-MANHATTAN PATTERNS USING VARIABLE SHAPED BEAM LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/429357 [patent_app_country] => US [patent_app_date] => 2012-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8008 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/429357
METHOD AND SYSTEM FOR FORMING NON-MANHATTAN PATTERNS USING VARIABLE SHAPED BEAM LITHOGRAPHY Mar 23, 2012 Abandoned
Array ( [id] => 9044350 [patent_doc_number] => 20130246988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR HIERARCHICAL FORMAL HARDWARE VERIFICATION OF FLOATING-POINT DIVISION AND/OR SQUARE ROOT ALGORITHMIC DESIGNS USING AUTOMATIC SEQUENTIAL EQUIVALENCE CHECKING' [patent_app_type] => utility [patent_app_number] => 13/423097 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13423097 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/423097
System, method, and computer program product for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking Mar 15, 2012 Issued
Array ( [id] => 9012595 [patent_doc_number] => 08527916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'Dissection splitting with optical proximity correction to reduce corner rounding' [patent_app_type] => utility [patent_app_number] => 13/419977 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419977
Dissection splitting with optical proximity correction to reduce corner rounding Mar 13, 2012 Issued
Array ( [id] => 8837304 [patent_doc_number] => 08453073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-28 [patent_title] => 'Method of mask generation for integrated circuit fabrication' [patent_app_type] => utility [patent_app_number] => 13/418480 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418480 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418480
Method of mask generation for integrated circuit fabrication Mar 12, 2012 Issued
Array ( [id] => 8946081 [patent_doc_number] => 08499268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Method of supporting layout design of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/404820 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4199 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404820 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404820
Method of supporting layout design of semiconductor integrated circuit Feb 23, 2012 Issued
Array ( [id] => 8395736 [patent_doc_number] => 20120233581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'DESIGN SUPPORT APPARATUS FOR SEMICONDUCTOR DEVICE, DESIGN SUPPORT PROGRAM, AND LAYOUT INFORMATION GENERATING METHOD' [patent_app_type] => utility [patent_app_number] => 13/402440 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8452 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/402440
DESIGN SUPPORT APPARATUS FOR SEMICONDUCTOR DEVICE, DESIGN SUPPORT PROGRAM, AND LAYOUT INFORMATION GENERATING METHOD Feb 21, 2012 Abandoned
Array ( [id] => 8741307 [patent_doc_number] => 08413095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-02 [patent_title] => 'Statistical single library including on chip variation for rapid timing and power analysis' [patent_app_type] => utility [patent_app_number] => 13/400680 [patent_app_country] => US [patent_app_date] => 2012-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6884 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13400680 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/400680
Statistical single library including on chip variation for rapid timing and power analysis Feb 20, 2012 Issued
Array ( [id] => 8655577 [patent_doc_number] => 08375345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Soft-bounded hierarchical synthesis' [patent_app_type] => utility [patent_app_number] => 13/398490 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5592 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13398490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/398490
Soft-bounded hierarchical synthesis Feb 15, 2012 Issued
Array ( [id] => 8861646 [patent_doc_number] => 08464200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-11 [patent_title] => 'Thermal relief optimization' [patent_app_type] => utility [patent_app_number] => 13/397510 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6335 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397510 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397510
Thermal relief optimization Feb 14, 2012 Issued
Array ( [id] => 9102881 [patent_doc_number] => 08566775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Graphic rendering of circuit positions' [patent_app_type] => utility [patent_app_number] => 13/350295 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13350295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/350295
Graphic rendering of circuit positions Jan 12, 2012 Issued
Menu