
Patrick G. Wamsley
Examiner (ID: 13217)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2514, 2819, 2753, 2513 |
| Total Applications | 980 |
| Issued Applications | 852 |
| Pending Applications | 37 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7646778
[patent_doc_number] => 06476740
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Z-coder: a fast adaptive binary arithmetic coder'
[patent_app_type] => B1
[patent_app_number] => 10/014907
[patent_app_country] => US
[patent_app_date] => 2001-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5165
[patent_no_of_claims] => 52
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[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/476/06476740.pdf
[firstpage_image] =>[orig_patent_app_number] => 10014907
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/014907 | Z-coder: a fast adaptive binary arithmetic coder | Dec 13, 2001 | Issued |
Array
(
[id] => 6124968
[patent_doc_number] => 20020075172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Device for encoding n-bit source words into corresponding m-bit channel words and decoding m-bit channel words into corresponding n-bit source words.'
[patent_app_type] => new
[patent_app_number] => 10/016168
[patent_app_country] => US
[patent_app_date] => 2001-12-10
[patent_effective_date] => 0000-00-00
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[patent_no_of_claims] => 23
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
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[pdf_file] => publications/A1/0075/20020075172.pdf
[firstpage_image] =>[orig_patent_app_number] => 10016168
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/016168 | Device for encoding n-bit source words into corresponding m-bit channel words and decoding m-bit channel words into corresponding n-bit source words. | Dec 9, 2001 | Abandoned |
Array
(
[id] => 1537434
[patent_doc_number] => 06489914
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'RSD analog to digital converter'
[patent_app_type] => B1
[patent_app_number] => 10/005275
[patent_app_country] => US
[patent_app_date] => 2001-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4205
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[firstpage_image] =>[orig_patent_app_number] => 10005275
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/005275 | RSD analog to digital converter | Dec 3, 2001 | Issued |
Array
(
[id] => 1384440
[patent_doc_number] => 06563445
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Self-calibration methods and structures for pipelined analog-to-digital converters'
[patent_app_type] => B1
[patent_app_number] => 09/995967
[patent_app_country] => US
[patent_app_date] => 2001-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 4928
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/995967 | Self-calibration methods and structures for pipelined analog-to-digital converters | Nov 27, 2001 | Issued |
Array
(
[id] => 1292584
[patent_doc_number] => 06633247
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[patent_kind] => B2
[patent_issue_date] => 2003-10-14
[patent_title] => 'Logarithmic a/d converter, method of logarithmic a/d conversion logarithmic d/a converter, method of logarithmic d/a conversion, and system for measuring physical quantity'
[patent_app_type] => B2
[patent_app_number] => 09/958567
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[patent_app_date] => 2001-11-27
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[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/633/06633247.pdf
[firstpage_image] =>[orig_patent_app_number] => 09958567
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/958567 | Logarithmic a/d converter, method of logarithmic a/d conversion logarithmic d/a converter, method of logarithmic d/a conversion, and system for measuring physical quantity | Nov 26, 2001 | Issued |
Array
(
[id] => 1401379
[patent_doc_number] => 06549151
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Method and apparatus for acquiring wide-band pseudorandom noise encoded waveforms'
[patent_app_type] => B1
[patent_app_number] => 09/995207
[patent_app_country] => US
[patent_app_date] => 2001-11-26
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[firstpage_image] =>[orig_patent_app_number] => 09995207
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/995207 | Method and apparatus for acquiring wide-band pseudorandom noise encoded waveforms | Nov 25, 2001 | Issued |
Array
(
[id] => 1368220
[patent_doc_number] => 06573849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-03
[patent_title] => 'Semiconductor device having a plurality of AD converters for inverter control of a motor and method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/987561
[patent_app_country] => US
[patent_app_date] => 2001-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3814
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[pdf_file] => patents/06/573/06573849.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/987561 | Semiconductor device having a plurality of AD converters for inverter control of a motor and method thereof | Nov 14, 2001 | Issued |
Array
(
[id] => 1183229
[patent_doc_number] => 06741193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-25
[patent_title] => 'Parallel in serial out circuit having flip-flop latching at multiple clock rates'
[patent_app_type] => B2
[patent_app_number] => 10/010073
[patent_app_country] => US
[patent_app_date] => 2001-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 5958
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[pdf_file] => patents/06/741/06741193.pdf
[firstpage_image] =>[orig_patent_app_number] => 10010073
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/010073 | Parallel in serial out circuit having flip-flop latching at multiple clock rates | Nov 7, 2001 | Issued |
Array
(
[id] => 1303989
[patent_doc_number] => 06624761
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-23
[patent_title] => 'Content independent data compression method and system'
[patent_app_type] => B2
[patent_app_number] => 10/016355
[patent_app_country] => US
[patent_app_date] => 2001-10-29
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[patent_drawing_sheets_cnt] => 34
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[pdf_file] => patents/06/624/06624761.pdf
[firstpage_image] =>[orig_patent_app_number] => 10016355
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/016355 | Content independent data compression method and system | Oct 28, 2001 | Issued |
Array
(
[id] => 6868205
[patent_doc_number] => 20030080894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => 'A/D converter'
[patent_app_type] => new
[patent_app_number] => 09/983658
[patent_app_country] => US
[patent_app_date] => 2001-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => publications/A1/0080/20030080894.pdf
[firstpage_image] =>[orig_patent_app_number] => 09983658
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/983658 | Analog to digital converter selecting reference voltages in accordance with feedback from prior stages | Oct 24, 2001 | Issued |
Array
(
[id] => 6868201
[patent_doc_number] => 20030080890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => 'Broadband IF conversion using two ADCs'
[patent_app_type] => new
[patent_app_number] => 09/982472
[patent_app_country] => US
[patent_app_date] => 2001-10-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/982472 | Broadband IF conversion using two ADCs | Oct 17, 2001 | Issued |
Array
(
[id] => 1441610
[patent_doc_number] => 06496126
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[patent_issue_date] => 2002-12-17
[patent_title] => 'Digitization apparatus and method using a finite state machine in feedback loop'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/981861 | Digitization apparatus and method using a finite state machine in feedback loop | Oct 16, 2001 | Issued |
Array
(
[id] => 6743460
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[patent_issue_date] => 2003-01-30
[patent_title] => 'Method and chip design for increasing yield of analogue/digital converter chips'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/976761 | Method and chip design for increasing yield of analogue/digital converter chips | Oct 11, 2001 | Abandoned |
Array
(
[id] => 6205976
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[patent_issue_date] => 2002-06-13
[patent_title] => 'Data slicer circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/975576 | Differential input data slicer | Oct 10, 2001 | Issued |
Array
(
[id] => 6154739
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[patent_title] => 'Single-bit sigma-delta modulated fractional-N frequency synthesizer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/973072 | Single-bit sigma-delta modulated fractional-N frequency synthesizer | Oct 9, 2001 | Abandoned |
Array
(
[id] => 1389189
[patent_doc_number] => 06559786
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[patent_issue_date] => 2003-05-06
[patent_title] => 'Circuit arrangement for conversion of an input current signal to a corresponding digital output signal'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/973371 | Circuit arrangement for conversion of an input current signal to a corresponding digital output signal | Oct 8, 2001 | Issued |
Array
(
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Array
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Array
(
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Array
(
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[pdf_file] => publications/A1/0005/20020005792.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/950783 | Encoding and decoding apparatus using context | Sep 12, 2001 | Issued |