Patrick G. Wamsley

Array ( [id] => 3897916 [patent_doc_number] => 05805883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Interrupt process distributing system' [patent_app_type] => 1 [patent_app_number] => 8/815071 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5780 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805883.pdf [firstpage_image] =>[orig_patent_app_number] => 815071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768314 [patent_doc_number] => 05721937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method and apparatus for reducing power consumption in a computer system by placing the CPU in a low power mode' [patent_app_type] => 1 [patent_app_number] => 8/810548 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721937.pdf [firstpage_image] =>[orig_patent_app_number] => 810548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768270 [patent_doc_number] => 05721934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Retrofit external power saving system and method for use' [patent_app_type] => 1 [patent_app_number] => 8/790275 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6854 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721934.pdf [firstpage_image] =>[orig_patent_app_number] => 790275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3839534 [patent_doc_number] => 05732250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Multi-function microprocessor wait state mechanism using external control line' [patent_app_type] => 1 [patent_app_number] => 8/786393 [patent_app_country] => US [patent_app_date] => 1997-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732250.pdf [firstpage_image] =>[orig_patent_app_number] => 786393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3812167 [patent_doc_number] => 05781781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Computer system including a novel CMOS voltage regulator' [patent_app_type] => 1 [patent_app_number] => 8/778580 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2277 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781781.pdf [firstpage_image] =>[orig_patent_app_number] => 778580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3936044 [patent_doc_number] => 05915122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Activation of a magnetic disk apparatus' [patent_app_type] => 1 [patent_app_number] => 8/798041 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 71 [patent_no_of_words] => 27994 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915122.pdf [firstpage_image] =>[orig_patent_app_number] => 798041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849372 [patent_doc_number] => 05815677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Buffer reservation method for a bus bridge system' [patent_app_type] => 1 [patent_app_number] => 8/774746 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9727 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815677.pdf [firstpage_image] =>[orig_patent_app_number] => 774746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3802742 [patent_doc_number] => 05737546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'System bus with separate address and data bus protocols' [patent_app_type] => 1 [patent_app_number] => 8/775552 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 17789 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737546.pdf [firstpage_image] =>[orig_patent_app_number] => 775552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788875 [patent_doc_number] => 05774741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Portable computer having a port connector for communicating with a variety of optional extension modules' [patent_app_type] => 1 [patent_app_number] => 8/777135 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774741.pdf [firstpage_image] =>[orig_patent_app_number] => 777135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3787957 [patent_doc_number] => 05774679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement' [patent_app_type] => 1 [patent_app_number] => 8/774614 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5190 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774679.pdf [firstpage_image] =>[orig_patent_app_number] => 774614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893527 [patent_doc_number] => 05729702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Multi-level round robin arbitration system' [patent_app_type] => 1 [patent_app_number] => 8/772782 [patent_app_country] => US [patent_app_date] => 1996-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3394 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729702.pdf [firstpage_image] =>[orig_patent_app_number] => 772782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788362 [patent_doc_number] => 05774706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'High speed PCI bus utilizing TTL compatible signaling' [patent_app_type] => 1 [patent_app_number] => 8/766914 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3047 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774706.pdf [firstpage_image] =>[orig_patent_app_number] => 766914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3903405 [patent_doc_number] => 05724592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Method and apparatus for managing active power consumption in a microprocessor controlled storage device' [patent_app_type] => 1 [patent_app_number] => 8/760325 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3942 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724592.pdf [firstpage_image] =>[orig_patent_app_number] => 760325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3641768 [patent_doc_number] => 05687319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Method and system for determining maximum cable segments between all possible node to node paths on a serial bus' [patent_app_type] => 1 [patent_app_number] => 8/761058 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5043 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687319.pdf [firstpage_image] =>[orig_patent_app_number] => 761058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3795712 [patent_doc_number] => 05758073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Serial interface between DSP and analog front-end device' [patent_app_type] => 1 [patent_app_number] => 8/755872 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758073.pdf [firstpage_image] =>[orig_patent_app_number] => 755872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3895043 [patent_doc_number] => 05799191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Method and apparatus for supporting cooperative works via computer network' [patent_app_type] => 1 [patent_app_number] => 8/756364 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6769 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799191.pdf [firstpage_image] =>[orig_patent_app_number] => 756364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3796196 [patent_doc_number] => 05758106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Arbitration unit which requests control of the system bus prior to determining whether such control is required' [patent_app_type] => 1 [patent_app_number] => 8/741084 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9466 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758106.pdf [firstpage_image] =>[orig_patent_app_number] => 741084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849530 [patent_doc_number] => 05761457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Inter-chip bus with fair access for multiple data pipes' [patent_app_type] => 1 [patent_app_number] => 8/731825 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15047 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761457.pdf [firstpage_image] =>[orig_patent_app_number] => 731825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894995 [patent_doc_number] => 05764997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'System for generating interrupt requests from either side of an inter-chip bus' [patent_app_type] => 1 [patent_app_number] => 8/734725 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15201 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764997.pdf [firstpage_image] =>[orig_patent_app_number] => 734725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3828672 [patent_doc_number] => 05771360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'PCI bus to target integrated circuit interconnect mechanism allowing multiple bus masters and two different protocols on the same bus' [patent_app_type] => 1 [patent_app_number] => 8/731829 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15211 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771360.pdf [firstpage_image] =>[orig_patent_app_number] => 731829 [rel_patent_id] =>[rel_patent_doc_number] =>)