Patrick G. Wamsley

Array ( [id] => 5724815 [patent_doc_number] => 20060055575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Analog-to-digital conversion arrangement, a method for analog-to-digital conversion and a signal processing system, in which the conversion arrangement is applied' [patent_app_type] => utility [patent_app_number] => 10/542136 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4560 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20060055575.pdf [firstpage_image] =>[orig_patent_app_number] => 10542136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7621894 [patent_doc_number] => 06977607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'SAR with partial capacitor sampling to reduce parasitic capacitance' [patent_app_type] => utility [patent_app_number] => 10/752930 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 10170 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977607.pdf [firstpage_image] =>[orig_patent_app_number] => 10752930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7240077 [patent_doc_number] => 20050140536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Clocking scheme for an algorithmic analog-to-digital converter' [patent_app_type] => utility [patent_app_number] => 10/749570 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6381 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140536.pdf [firstpage_image] =>[orig_patent_app_number] => 10749570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7262098 [patent_doc_number] => 20040150544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'ANALOG TO DIGITAL CONVERTER WITH INTERPOLATION OF REFERENCE LADDER' [patent_app_type] => new [patent_app_number] => 10/748250 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4291 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150544.pdf [firstpage_image] =>[orig_patent_app_number] => 10748250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700994 [patent_doc_number] => 07068202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Architecture for an algorithmic analog-to-digital converter' [patent_app_type] => utility [patent_app_number] => 10/749571 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5669 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068202.pdf [firstpage_image] =>[orig_patent_app_number] => 10749571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 767776 [patent_doc_number] => 07009545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Semiconductor device having on-chip reference voltage generator' [patent_app_type] => utility [patent_app_number] => 10/750078 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3452 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009545.pdf [firstpage_image] =>[orig_patent_app_number] => 10750078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959219 [patent_doc_number] => 06954167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Common centroid layout for parallel resistors in an amplifier with matched AC performance' [patent_app_type] => utility [patent_app_number] => 10/735387 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 10218 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954167.pdf [firstpage_image] =>[orig_patent_app_number] => 10735387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959222 [patent_doc_number] => 06954170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Open loop common mode driver for switched capacitor input to SAR' [patent_app_type] => utility [patent_app_number] => 10/734854 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 9933 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954170.pdf [firstpage_image] =>[orig_patent_app_number] => 10734854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 964239 [patent_doc_number] => 06950052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Noise cancellation in a single ended SAR converter' [patent_app_type] => utility [patent_app_number] => 10/735163 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 9953 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950052.pdf [firstpage_image] =>[orig_patent_app_number] => 10735163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 791076 [patent_doc_number] => 06985101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'High speed comparator with blocking switches for SAR convertor' [patent_app_type] => utility [patent_app_number] => 10/735164 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 10072 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985101.pdf [firstpage_image] =>[orig_patent_app_number] => 10735164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 956766 [patent_doc_number] => 06956520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'SAR data converter with unequal clock pulses for MSBS to allow for settling' [patent_app_type] => utility [patent_app_number] => 10/734890 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 9988 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/956/06956520.pdf [firstpage_image] =>[orig_patent_app_number] => 10734890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 780207 [patent_doc_number] => 06995693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Method and apparatus for multiple input diversity decoding' [patent_app_type] => utility [patent_app_number] => 10/728076 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2912 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995693.pdf [firstpage_image] =>[orig_patent_app_number] => 10728076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7627642 [patent_doc_number] => 06806796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'End-surface reflection type surface acoustic wave filter' [patent_app_type] => B2 [patent_app_number] => 10/725872 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5388 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806796.pdf [firstpage_image] =>[orig_patent_app_number] => 10725872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6937103 [patent_doc_number] => 20050110664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Suppressing digital-to-analog converter (DAC) error' [patent_app_type] => utility [patent_app_number] => 10/723472 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4617 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110664.pdf [firstpage_image] =>[orig_patent_app_number] => 10723472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6937102 [patent_doc_number] => 20050110663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method to efficiently generate the row and column index for half rate interleaver in GSM' [patent_app_type] => utility [patent_app_number] => 10/719079 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6155 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110663.pdf [firstpage_image] =>[orig_patent_app_number] => 10719079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7287080 [patent_doc_number] => 20040108945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Encoder, decoder, and data transfer system' [patent_app_type] => new [patent_app_number] => 10/716678 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 24458 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20040108945.pdf [firstpage_image] =>[orig_patent_app_number] => 10716678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 681731 [patent_doc_number] => 07084789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'DC-free code having limited error propagation and limited complexity' [patent_app_type] => utility [patent_app_number] => 10/715077 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4277 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084789.pdf [firstpage_image] =>[orig_patent_app_number] => 10715077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 786108 [patent_doc_number] => 06989776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Generation of interleaved parity code words having limited running digital sum values' [patent_app_type] => utility [patent_app_number] => 10/715078 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7603 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989776.pdf [firstpage_image] =>[orig_patent_app_number] => 10715078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 941724 [patent_doc_number] => 06970116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Multiplexer circuit for converting parallel data into serial data at high speed and synchronizing the serial data with a clock signal' [patent_app_type] => utility [patent_app_number] => 10/705977 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5453 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970116.pdf [firstpage_image] =>[orig_patent_app_number] => 10705977 [rel_patent_id] =>[rel_patent_doc_number] =>)