Search

Patrick G. Wamsley

Examiner (ID: 13217)

Most Active Art Unit
2819
Art Unit(s)
2514, 2819, 2753, 2513
Total Applications
980
Issued Applications
852
Pending Applications
37
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7335091 [patent_doc_number] => 20040189347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Robust variable keeper strength process-compensated dynamic circuit and method' [patent_app_type] => new [patent_app_number] => 10/401774 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7045 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20040189347.pdf [firstpage_image] =>[orig_patent_app_number] => 10401774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/401774
Robust variable keeper strength process-compensated dynamic circuit and method Mar 30, 2003 Issued
Array ( [id] => 1074242 [patent_doc_number] => 06838908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits' [patent_app_type] => utility [patent_app_number] => 10/400873 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5124 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838908.pdf [firstpage_image] =>[orig_patent_app_number] => 10400873 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/400873
Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits Mar 27, 2003 Issued
Array ( [id] => 1172028 [patent_doc_number] => 06756929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Methods and structures for interleavably processing data and error signals in pipelined analog-to-digital converter systems' [patent_app_type] => B1 [patent_app_number] => 10/402277 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6563 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756929.pdf [firstpage_image] =>[orig_patent_app_number] => 10402277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/402277
Methods and structures for interleavably processing data and error signals in pipelined analog-to-digital converter systems Mar 26, 2003 Issued
Array ( [id] => 1106773 [patent_doc_number] => 06812735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Multiple value self-calibrated termination resistors' [patent_app_type] => B1 [patent_app_number] => 10/397496 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812735.pdf [firstpage_image] =>[orig_patent_app_number] => 10397496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397496
Multiple value self-calibrated termination resistors Mar 25, 2003 Issued
Array ( [id] => 1133450 [patent_doc_number] => 06788106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data' [patent_app_type] => B2 [patent_app_number] => 10/397773 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9129 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788106.pdf [firstpage_image] =>[orig_patent_app_number] => 10397773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397773
Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data Mar 25, 2003 Issued
Array ( [id] => 1066592 [patent_doc_number] => 06847225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'CML (current mode logic) OCD (off chip driver)—ODT (on die termination) circuit for bidirectional data transmission' [patent_app_type] => utility [patent_app_number] => 10/394779 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3980 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847225.pdf [firstpage_image] =>[orig_patent_app_number] => 10394779 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/394779
CML (current mode logic) OCD (off chip driver)—ODT (on die termination) circuit for bidirectional data transmission Mar 20, 2003 Issued
Array ( [id] => 1054131 [patent_doc_number] => 06859072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Method for clock control of clocked half-rail differential logic with sense amplifier and single-rail logic' [patent_app_type] => utility [patent_app_number] => 10/394880 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9491 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859072.pdf [firstpage_image] =>[orig_patent_app_number] => 10394880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/394880
Method for clock control of clocked half-rail differential logic with sense amplifier and single-rail logic Mar 19, 2003 Issued
Array ( [id] => 935786 [patent_doc_number] => 06975136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Isolated channel in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/393191 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1731 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975136.pdf [firstpage_image] =>[orig_patent_app_number] => 10393191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/393191
Isolated channel in an integrated circuit Mar 19, 2003 Issued
Array ( [id] => 7423740 [patent_doc_number] => 20040183564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Programmable logic devices with integrated standard-cell logic blocks' [patent_app_type] => new [patent_app_number] => 10/391094 [patent_app_country] => US [patent_app_date] => 2003-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7446 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183564.pdf [firstpage_image] =>[orig_patent_app_number] => 10391094 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/391094
Programmable logic devices with integrated standard-cell logic blocks Mar 17, 2003 Issued
Array ( [id] => 7284636 [patent_doc_number] => 20040145937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Semiconductor integrated circuit device having flip-flops that can be reset easily' [patent_app_type] => new [patent_app_number] => 10/389876 [patent_app_country] => US [patent_app_date] => 2003-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145937.pdf [firstpage_image] =>[orig_patent_app_number] => 10389876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/389876
Semiconductor integrated circuit device having flip-flops that can be reset easily Mar 17, 2003 Issued
Array ( [id] => 731378 [patent_doc_number] => 07042377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Analog-to-digital sigma-delta modulator with FIR filter feedback' [patent_app_type] => utility [patent_app_number] => 10/381075 [patent_app_country] => US [patent_app_date] => 2003-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5514 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042377.pdf [firstpage_image] =>[orig_patent_app_number] => 10381075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/381075
Analog-to-digital sigma-delta modulator with FIR filter feedback Mar 17, 2003 Issued
Array ( [id] => 1057225 [patent_doc_number] => 06856166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Status scheme signal processing circuit' [patent_app_type] => utility [patent_app_number] => 10/388497 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2310 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856166.pdf [firstpage_image] =>[orig_patent_app_number] => 10388497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388497
Status scheme signal processing circuit Mar 16, 2003 Issued
Array ( [id] => 1134119 [patent_doc_number] => 06788229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Margining pin interface circuit for clock adjustment of digital to analog converter' [patent_app_type] => B1 [patent_app_number] => 10/389374 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788229.pdf [firstpage_image] =>[orig_patent_app_number] => 10389374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/389374
Margining pin interface circuit for clock adjustment of digital to analog converter Mar 13, 2003 Issued
Array ( [id] => 7377249 [patent_doc_number] => 20040178838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Variable pulse width and pulse separation clock generator' [patent_app_type] => new [patent_app_number] => 10/388977 [patent_app_country] => US [patent_app_date] => 2003-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5158 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178838.pdf [firstpage_image] =>[orig_patent_app_number] => 10388977 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388977
Variable pulse width and pulse separation clock generator Mar 12, 2003 Issued
Array ( [id] => 7377183 [patent_doc_number] => 20040178825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'MULTISTAGE, SINGLE-RAIL LOGIC CIRCUITRY AND METHOD THEREFORE' [patent_app_type] => new [patent_app_number] => 10/388974 [patent_app_country] => US [patent_app_date] => 2003-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5779 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178825.pdf [firstpage_image] =>[orig_patent_app_number] => 10388974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388974
Multistage, single-rail logic circuitry and method therefore Mar 12, 2003 Issued
Array ( [id] => 6727712 [patent_doc_number] => 20030183902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Integrated circuit schematic for current switching of a constant current source' [patent_app_type] => new [patent_app_number] => 10/388192 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1262 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20030183902.pdf [firstpage_image] =>[orig_patent_app_number] => 10388192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388192
Integrated circuit schematic for current switching of a constant current source Mar 11, 2003 Abandoned
Array ( [id] => 1009903 [patent_doc_number] => 06900667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Logic constructions and electronic devices' [patent_app_type] => utility [patent_app_number] => 10/387090 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 10918 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900667.pdf [firstpage_image] =>[orig_patent_app_number] => 10387090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/387090
Logic constructions and electronic devices Mar 10, 2003 Issued
Array ( [id] => 6826309 [patent_doc_number] => 20030236931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Data transfer control circuitry including fifo buffers' [patent_app_type] => new [patent_app_number] => 10/379799 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5465 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20030236931.pdf [firstpage_image] =>[orig_patent_app_number] => 10379799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379799
Data transfer control circuitry including FIFO buffers Mar 5, 2003 Issued
Array ( [id] => 7271327 [patent_doc_number] => 20040059845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Simultaneous bidirectional input/output circuit' [patent_app_type] => new [patent_app_number] => 10/379781 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5160 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059845.pdf [firstpage_image] =>[orig_patent_app_number] => 10379781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379781
Simultaneous bidirectional input/output circuit Mar 3, 2003 Issued
Array ( [id] => 7614844 [patent_doc_number] => 06897684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Input buffer circuit and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/379200 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4254 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897684.pdf [firstpage_image] =>[orig_patent_app_number] => 10379200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379200
Input buffer circuit and semiconductor memory device Mar 3, 2003 Issued
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