Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17115542 [patent_doc_number] => 20210296139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR DEVICE WITH TIERED PILLAR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/340298 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340298
Semiconductor device with tiered pillar and manufacturing method thereof Jun 6, 2021 Issued
Array ( [id] => 18190854 [patent_doc_number] => 11581459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Light-emitting device having a recess defined by a base and lateral surfaces of a first and a second wall [patent_app_type] => utility [patent_app_number] => 17/339120 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4566 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339120
Light-emitting device having a recess defined by a base and lateral surfaces of a first and a second wall Jun 3, 2021 Issued
Array ( [id] => 18061784 [patent_doc_number] => 20220392871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/338600 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338600
Semiconductor package Jun 2, 2021 Issued
Array ( [id] => 18549886 [patent_doc_number] => 11723259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Substrate processing apparatus and method of processing substrate [patent_app_type] => utility [patent_app_number] => 17/336657 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6910 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336657
Substrate processing apparatus and method of processing substrate Jun 1, 2021 Issued
Array ( [id] => 19901519 [patent_doc_number] => 12279472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Quantum dot light emitting diode, method for manufacturing the same, and display device [patent_app_type] => utility [patent_app_number] => 17/772612 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4801 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17772612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/772612
Quantum dot light emitting diode, method for manufacturing the same, and display device May 30, 2021 Issued
Array ( [id] => 18804345 [patent_doc_number] => 11837508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Method of forming high-k dielectric material [patent_app_type] => utility [patent_app_number] => 17/603176 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5073 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17603176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/603176
Method of forming high-k dielectric material May 24, 2021 Issued
Array ( [id] => 17070835 [patent_doc_number] => 20210273052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => BIPOLAR-TRANSISTOR DEVICE AND CORRESPONDING FABRICATION PROCESS [patent_app_type] => utility [patent_app_number] => 17/323170 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323170
Bipolar-transistor device and corresponding fabrication process May 17, 2021 Issued
Array ( [id] => 18609932 [patent_doc_number] => 11751431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Display apparatus and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/323161 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323161
Display apparatus and electronic device including the same May 17, 2021 Issued
Array ( [id] => 17509177 [patent_doc_number] => 20220102280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Very Fine Pitch and Wiring Density Organic Side by Side Chiplet Integration [patent_app_type] => utility [patent_app_number] => 17/321080 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321080
Very fine pitch and wiring density organic side by side chiplet integration May 13, 2021 Issued
Array ( [id] => 18088668 [patent_doc_number] => 11538807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for fabricating a semiconductor device including a gate structure with an inclined side wall [patent_app_type] => utility [patent_app_number] => 17/318133 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 11048 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318133
Method for fabricating a semiconductor device including a gate structure with an inclined side wall May 11, 2021 Issued
Array ( [id] => 18494247 [patent_doc_number] => 11699668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Semiconductor device package having warpage control and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/318139 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318139
Semiconductor device package having warpage control and method of forming the same May 11, 2021 Issued
Array ( [id] => 18704710 [patent_doc_number] => 11791227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Electronic device package [patent_app_type] => utility [patent_app_number] => 17/317770 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 7092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317770
Electronic device package May 10, 2021 Issued
Array ( [id] => 17993193 [patent_doc_number] => 20220359230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => ENCAPSULATION WARPAGE REDUCTION FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/315588 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315588
Encapsulation warpage reduction for semiconductor die assemblies and associated methods and systems May 9, 2021 Issued
Array ( [id] => 18219542 [patent_doc_number] => 11594491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Multi-die interconnect [patent_app_type] => utility [patent_app_number] => 17/245903 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 10073 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245903
Multi-die interconnect Apr 29, 2021 Issued
Array ( [id] => 20216146 [patent_doc_number] => 12412800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Integrated circuit package having enhanced thermal dissipation structure [patent_app_type] => utility [patent_app_number] => 17/239776 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239776
Integrated circuit package having enhanced thermal dissipation structure Apr 25, 2021 Issued
Array ( [id] => 17963649 [patent_doc_number] => 20220344230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/239478 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239478
Semiconductor device package Apr 22, 2021 Issued
Array ( [id] => 17010974 [patent_doc_number] => 20210242135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => DISPLAY DEVICES AND METHODS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/237154 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237154
DISPLAY DEVICES AND METHODS FOR MANUFACTURING THE SAME Apr 21, 2021 Abandoned
Array ( [id] => 18464442 [patent_doc_number] => 11688738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Composite transistor with electrodes extending to active regions [patent_app_type] => utility [patent_app_number] => 17/233753 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 15227 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233753 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233753
Composite transistor with electrodes extending to active regions Apr 18, 2021 Issued
Array ( [id] => 17855212 [patent_doc_number] => 20220285255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => WIRING BOARD WITH EMBEDDED INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/232109 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232109
Wiring board with interposer substrate surrounded by underfill and embedded in main substrate and method of fabricating the same Apr 14, 2021 Issued
Array ( [id] => 18349811 [patent_doc_number] => 20230137922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ARRAY SUBSTRATE, MANUFACTURING PROCESS OF ARRAY SUBSTRATE, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/287169 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/287169
Array substrate including photosensitive element and display panel Apr 13, 2021 Issued
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