Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17908593 [patent_doc_number] => 11462454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor package comprising heat spreader and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/158386 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2455 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158386
Semiconductor package comprising heat spreader and manufacturing method thereof Jan 25, 2021 Issued
Array ( [id] => 17862897 [patent_doc_number] => 11444058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Package structure with separated street between chips [patent_app_type] => utility [patent_app_number] => 17/152806 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152806
Package structure with separated street between chips Jan 19, 2021 Issued
Array ( [id] => 16812491 [patent_doc_number] => 20210135046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => COMPONENT HAVING METAL CARRIER LAYER AND REDUCED OVERALL HEIGHT [patent_app_type] => utility [patent_app_number] => 17/148208 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148208
Component having metal carrier layer and layer that compensates for internal mechanical strains Jan 12, 2021 Issued
Array ( [id] => 18105512 [patent_doc_number] => 11545409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Semiconductor module having block electrode bonded to collector electrode and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/141990 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141990
Semiconductor module having block electrode bonded to collector electrode and manufacturing method thereof Jan 4, 2021 Issued
Array ( [id] => 20115481 [patent_doc_number] => 12365167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Encapsulation film having excellent reliability, organic electronic device comprising the same, and method for manufacturing organic electronic device [patent_app_type] => utility [patent_app_number] => 17/787050 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 7460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/787050
Encapsulation film having excellent reliability, organic electronic device comprising the same, and method for manufacturing organic electronic device Jan 3, 2021 Issued
Array ( [id] => 17772408 [patent_doc_number] => 11404360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Power module with enhanced heat dissipation [patent_app_type] => utility [patent_app_number] => 17/139571 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 4522 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139571
Power module with enhanced heat dissipation Dec 30, 2020 Issued
Array ( [id] => 18190640 [patent_doc_number] => 11581241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Circuit modules with front-side interposer terminals and through-module thermal dissipation structures [patent_app_type] => utility [patent_app_number] => 17/136408 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 16053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136408
Circuit modules with front-side interposer terminals and through-module thermal dissipation structures Dec 28, 2020 Issued
Array ( [id] => 16781743 [patent_doc_number] => 20210118822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/135285 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135285
Semiconductor device with a substrate having depressions formed thereon Dec 27, 2020 Issued
Array ( [id] => 17477677 [patent_doc_number] => 20220085181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => METHOD OF FORMING TOP SELECT GATE TRENCHES [patent_app_type] => utility [patent_app_number] => 17/132802 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132802
Method of forming top select gate trenches Dec 22, 2020 Issued
Array ( [id] => 18548278 [patent_doc_number] => 11721638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Optically detectable reference feature for processing a semiconductor wafer [patent_app_type] => utility [patent_app_number] => 17/126743 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126743
Optically detectable reference feature for processing a semiconductor wafer Dec 17, 2020 Issued
Array ( [id] => 19733773 [patent_doc_number] => 12211775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Multiple substrate package systems and related methods [patent_app_type] => utility [patent_app_number] => 17/126433 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126433
Multiple substrate package systems and related methods Dec 17, 2020 Issued
Array ( [id] => 19095525 [patent_doc_number] => 11957009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Display device having circuit member stably bonded onto display substrate [patent_app_type] => utility [patent_app_number] => 17/115155 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 12209 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115155
Display device having circuit member stably bonded onto display substrate Dec 7, 2020 Issued
Array ( [id] => 17908590 [patent_doc_number] => 11462451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor device having terminals including heat dissipation portions, and method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/115322 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2967 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115322
Semiconductor device having terminals including heat dissipation portions, and method of manufacturing thereof Dec 7, 2020 Issued
Array ( [id] => 18520795 [patent_doc_number] => 11710689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor device package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/115629 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6994 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115629
Semiconductor device package and method of manufacturing the same Dec 7, 2020 Issued
Array ( [id] => 18126472 [patent_doc_number] => 20230012093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => NON-VOLATILE STORAGE DEVICE, NON-VOLATILE STORAGE ELEMENT, AND MANUFACTURING METHOD FOR THEIR PRODUCTION [patent_app_type] => utility [patent_app_number] => 17/781803 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/781803
Non-volatile ferroelectric storage element and devices comprising them Dec 3, 2020 Issued
Array ( [id] => 17847929 [patent_doc_number] => 11437314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Semiconductor device with anti-fuse and metal-insulator-metal (MIM) capacitor connected to redistribution layer (RDL) and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/107035 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8369 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107035
Semiconductor device with anti-fuse and metal-insulator-metal (MIM) capacitor connected to redistribution layer (RDL) and method for forming the same Nov 29, 2020 Issued
Array ( [id] => 17630606 [patent_doc_number] => 20220165621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => METHODS OF FORMING THROUGH-SILICON VIAS IN SUBSTRATES FOR ADVANCED PACKAGING [patent_app_type] => utility [patent_app_number] => 16/953869 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953869
Methods of forming through-silicon vias in substrates for advanced packaging Nov 19, 2020 Issued
Array ( [id] => 17668316 [patent_doc_number] => 11362020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Flipchip package with an IC having a covered cavity comprising metal posts [patent_app_type] => utility [patent_app_number] => 17/098930 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3661 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098930
Flipchip package with an IC having a covered cavity comprising metal posts Nov 15, 2020 Issued
Array ( [id] => 17878506 [patent_doc_number] => 11450529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface [patent_app_type] => utility [patent_app_number] => 17/096444 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 12669 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096444
Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface Nov 11, 2020 Issued
Array ( [id] => 18120622 [patent_doc_number] => 11552021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Semiconductor device, semiconductor manufacturing apparatus and method of manufacturing semiconductor device having printed circuit board and insulating board with complementary warps [patent_app_type] => utility [patent_app_number] => 17/093998 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 39 [patent_no_of_words] => 12582 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093998
Semiconductor device, semiconductor manufacturing apparatus and method of manufacturing semiconductor device having printed circuit board and insulating board with complementary warps Nov 9, 2020 Issued
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