Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16120263 [patent_doc_number] => 20200212154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/719219 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719219
Light emitting display device Dec 17, 2019 Issued
Array ( [id] => 16098607 [patent_doc_number] => 20200203290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => Through Wafer Trench Isolation and Capacitive Coupling [patent_app_type] => utility [patent_app_number] => 16/717262 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717262
Through wafer trench isolation between transistors in an integrated circuit Dec 16, 2019 Issued
Array ( [id] => 16098951 [patent_doc_number] => 20200203462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => DISPLAY DEVICE AND APPARATUS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/716275 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716275 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716275
Display device for preventing cracks caused by bending stress and apparatus for manufacturing the same for reducing number of mask process Dec 15, 2019 Issued
Array ( [id] => 17402932 [patent_doc_number] => 20220045023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR PACKAGE COMPONENT, BASE SUBSTRATE FOR RF TRANSISTOR, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/413403 [patent_app_country] => US [patent_app_date] => 2019-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413403
Semiconductor package component Nov 28, 2019 Issued
Array ( [id] => 16858455 [patent_doc_number] => 20210159200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/698671 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698671
Semiconductor device package having a core substrate and an embedded component in the core substrate Nov 26, 2019 Issued
Array ( [id] => 16417959 [patent_doc_number] => 10825860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Electrode configuration for an optoelectronic device [patent_app_type] => utility [patent_app_number] => 16/692790 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 8081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692790
Electrode configuration for an optoelectronic device Nov 21, 2019 Issued
Array ( [id] => 17590969 [patent_doc_number] => 11329246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Organic light emitting diode panel and method for fabricating same [patent_app_type] => utility [patent_app_number] => 16/625772 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3571 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625772
Organic light emitting diode panel and method for fabricating same Nov 21, 2019 Issued
Array ( [id] => 16249464 [patent_doc_number] => 10748839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Package structure of a folding magnetic coupling isolator, leadframe component, and leadframe structure [patent_app_type] => utility [patent_app_number] => 16/689234 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5849 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689234
Package structure of a folding magnetic coupling isolator, leadframe component, and leadframe structure Nov 19, 2019 Issued
Array ( [id] => 16324446 [patent_doc_number] => 10784422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Semiconductor device with optically-transmissive layer and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/686516 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 12891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686516 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686516
Semiconductor device with optically-transmissive layer and manufacturing method thereof Nov 17, 2019 Issued
Array ( [id] => 16456000 [patent_doc_number] => 20200365426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => HIGH-FREQUENCY HEATING DEVICE FOR MOUNTING LED [patent_app_type] => utility [patent_app_number] => 16/662178 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662178
HIGH-FREQUENCY HEATING DEVICE FOR MOUNTING LED Oct 23, 2019 Abandoned
Array ( [id] => 15745741 [patent_doc_number] => 20200111760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/583006 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583006
Semiconductor package including cap layer and dam structure and method of manufacturing the same Sep 24, 2019 Issued
Array ( [id] => 17152669 [patent_doc_number] => 11145760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Structure having improved fin critical dimension control [patent_app_type] => utility [patent_app_number] => 16/582572 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 10249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582572
Structure having improved fin critical dimension control Sep 24, 2019 Issued
Array ( [id] => 16348175 [patent_doc_number] => 20200312826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/583051 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583051 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583051
Semiconductor package including a substrate having two silicon layers formed on each other Sep 24, 2019 Issued
Array ( [id] => 16080689 [patent_doc_number] => 20200194331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/582418 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582418 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582418
Semiconductor packages including a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure Sep 24, 2019 Issued
Array ( [id] => 17196073 [patent_doc_number] => 11164840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Chip interconnection structure, wafer interconnection structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/582441 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5648 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582441
Chip interconnection structure, wafer interconnection structure and method for manufacturing the same Sep 24, 2019 Issued
Array ( [id] => 16684517 [patent_doc_number] => 10944009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Methods of fabricating a FinFET device with wrap-around silicide source/drain structure [patent_app_type] => utility [patent_app_number] => 16/582547 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 8569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582547
Methods of fabricating a FinFET device with wrap-around silicide source/drain structure Sep 24, 2019 Issued
Array ( [id] => 16944364 [patent_doc_number] => 11056617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Manufacturing method of light-emitting device having a recess defined by a base and lateral surfaces of a first and a second wall [patent_app_type] => utility [patent_app_number] => 16/582968 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4544 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582968
Manufacturing method of light-emitting device having a recess defined by a base and lateral surfaces of a first and a second wall Sep 24, 2019 Issued
Array ( [id] => 16601620 [patent_doc_number] => 20210028151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => Wafer Structure, Method For Manufacturing The Same, And Chip Structure [patent_app_type] => utility [patent_app_number] => 16/582620 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582620
Wafer structure with capacitive chip interconnection, method for manufacturing the same, and chip structure with capacitive chip interconnection Sep 24, 2019 Issued
Array ( [id] => 17181535 [patent_doc_number] => 11158786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => MRAM device formation with controlled ion beam etch of MTJ [patent_app_type] => utility [patent_app_number] => 16/582762 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582762 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582762
MRAM device formation with controlled ion beam etch of MTJ Sep 24, 2019 Issued
Array ( [id] => 16723883 [patent_doc_number] => 20210091030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => ELECTROLESS-CATALYST DOPED-MOLD MATERIALS FOR INTEGRATED-CIRCUIT DIE PACKAGING ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 16/582865 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582865
Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures Sep 24, 2019 Issued
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