
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18105506
[patent_doc_number] => 11545403
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-03
[patent_title] => Semiconductor package having a multilayer structure and a transport tray for the semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 17/250542
[patent_app_country] => US
[patent_app_date] => 2019-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 10253
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250542
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/250542 | Semiconductor package having a multilayer structure and a transport tray for the semiconductor structure | Jun 24, 2019 | Issued |
Array
(
[id] => 14938633
[patent_doc_number] => 20190304955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => Apparatuses Comprising Semiconductor Dies in Face-To-Face Arrangements
[patent_app_type] => utility
[patent_app_number] => 16/447749
[patent_app_country] => US
[patent_app_date] => 2019-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16944
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 422
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447749
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/447749 | Apparatuses comprising semiconductor dies in face-to-face arrangements | Jun 19, 2019 | Issued |
Array
(
[id] => 18950976
[patent_doc_number] => 11894282
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Vented lids for integrated circuit packages
[patent_app_type] => utility
[patent_app_number] => 16/446538
[patent_app_country] => US
[patent_app_date] => 2019-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 13167
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446538
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/446538 | Vented lids for integrated circuit packages | Jun 18, 2019 | Issued |
Array
(
[id] => 15611475
[patent_doc_number] => 10586807
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Arrays of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stacks
[patent_app_type] => utility
[patent_app_number] => 16/437781
[patent_app_country] => US
[patent_app_date] => 2019-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 5741
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437781
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/437781 | Arrays of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stacks | Jun 10, 2019 | Issued |
Array
(
[id] => 16516011
[patent_doc_number] => 20200395269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => CHANNELED LIDS FOR INTEGRATED CIRCUIT PACKAGES
[patent_app_type] => utility
[patent_app_number] => 16/437872
[patent_app_country] => US
[patent_app_date] => 2019-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437872
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/437872 | Channeled lids for integrated circuit packages | Jun 10, 2019 | Issued |
Array
(
[id] => 14904865
[patent_doc_number] => 20190296198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => LED ASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 16/436472
[patent_app_country] => US
[patent_app_date] => 2019-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436472
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/436472 | LED assembly | Jun 9, 2019 | Issued |
Array
(
[id] => 15260441
[patent_doc_number] => 20190378954
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => LIGHT-EMITTING ELEMENT, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE COMPRISING LIGHT-EMITTING ELEMENT
[patent_app_type] => utility
[patent_app_number] => 16/435313
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12285
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435313
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435313 | Light-emitting element, method of manufacturing the same and display device comprising light-emitting element | Jun 6, 2019 | Issued |
Array
(
[id] => 17137832
[patent_doc_number] => 11139401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-05
[patent_title] => Vertical thin film transistor structures with localized gate dielectric
[patent_app_type] => utility
[patent_app_number] => 16/435359
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 10038
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435359
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435359 | Vertical thin film transistor structures with localized gate dielectric | Jun 6, 2019 | Issued |
Array
(
[id] => 16509326
[patent_doc_number] => 20200388582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-10
[patent_title] => PSEUDO-STRIPLINE USING DOUBLE SOLDER-RESIST STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/435136
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6845
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435136
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435136 | Pseudo-stripline using double solder-resist structure | Jun 6, 2019 | Issued |
Array
(
[id] => 16509420
[patent_doc_number] => 20200388676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-10
[patent_title] => SEMICONDUCTOR DEVICE WITH CONDUCTING STRUCTURE FOR REDUCING PARASITIC CAPACITANCE AND IMPROVING RC DELAY
[patent_app_type] => utility
[patent_app_number] => 16/435102
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5624
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435102
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435102 | Semiconductor device with conducting structure for reducing parasitic capacitance and improving RC delay | Jun 6, 2019 | Issued |
Array
(
[id] => 17668495
[patent_doc_number] => 11362200
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-14
[patent_title] => Enhanced cascade field effect transistor
[patent_app_type] => utility
[patent_app_number] => 16/435457
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5241
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435457
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435457 | Enhanced cascade field effect transistor | Jun 6, 2019 | Issued |
Array
(
[id] => 16536692
[patent_doc_number] => 10879306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Micro semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 16/434786
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 9835
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16434786
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/434786 | Micro semiconductor structure | Jun 6, 2019 | Issued |
Array
(
[id] => 15030863
[patent_doc_number] => 20190326436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING
[patent_app_type] => utility
[patent_app_number] => 16/433626
[patent_app_country] => US
[patent_app_date] => 2019-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3724
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433626
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/433626 | FinFET with multilayer fins for multi-value logic (MVL) applications | Jun 5, 2019 | Issued |
Array
(
[id] => 17002663
[patent_doc_number] => 11081486
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-03
[patent_title] => Integrated circuit having memory cell array including barriers, and method of manufacturing same
[patent_app_type] => utility
[patent_app_number] => 16/424344
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 62
[patent_figures_cnt] => 94
[patent_no_of_words] => 11858
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424344
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424344 | Integrated circuit having memory cell array including barriers, and method of manufacturing same | May 27, 2019 | Issued |
Array
(
[id] => 16226362
[patent_doc_number] => 20200251479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-06
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CARBON-DOPED SOURCE CONTACT LAYER AND METHODS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/408722
[patent_app_country] => US
[patent_app_date] => 2019-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 45244
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408722
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/408722 | Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same | May 9, 2019 | Issued |
Array
(
[id] => 18999140
[patent_doc_number] => 11915996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling
[patent_app_type] => utility
[patent_app_number] => 16/407587
[patent_app_country] => US
[patent_app_date] => 2019-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 9617
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407587
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/407587 | Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling | May 8, 2019 | Issued |
Array
(
[id] => 16440417
[patent_doc_number] => 20200357744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => DISAGGREGATED DIE INTERCONNECTION WITH ON-SILICON CAVITY BRIDGE
[patent_app_type] => utility
[patent_app_number] => 16/405610
[patent_app_country] => US
[patent_app_date] => 2019-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6168
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405610
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/405610 | Disaggregated die interconnection with on-silicon cavity bridge | May 6, 2019 | Issued |
Array
(
[id] => 14722825
[patent_doc_number] => 20190252476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-15
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/396752
[patent_app_country] => US
[patent_app_date] => 2019-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396752
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/396752 | Display device having conductive line | Apr 27, 2019 | Issued |
Array
(
[id] => 16402363
[patent_doc_number] => 20200343221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-29
[patent_title] => DIE OVER MOLD STACKED SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/392295
[patent_app_country] => US
[patent_app_date] => 2019-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6922
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392295
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/392295 | Die over mold stacked semiconductor package | Apr 22, 2019 | Issued |
Array
(
[id] => 14691547
[patent_doc_number] => 20190244889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/385669
[patent_app_country] => US
[patent_app_date] => 2019-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385669
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/385669 | Semiconductor device manufacturing method including forming a wide portion spreading over a looped portion | Apr 15, 2019 | Issued |